// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  dmc_reg_offset_field.h
// Project line  :  
// Department    :  K5
// Author        :  AnthonySixta
// Version       :  1.0
// Date          :  2013/5/31
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  AnthonySixta 2018/03/16 17:45:55 Create file
// ******************************************************************************

#ifndef __DMC_REG_OFFSET_FIELD_H__
#define __DMC_REG_OFFSET_FIELD_H__

#define DMC_ASREF_EN_LEN     16
#define DMC_ASREF_EN_OFFSET  16
#define DMC_SREF_DONE_LEN    1
#define DMC_SREF_DONE_OFFSET 1
#define DMC_SREF_REQ_LEN     1
#define DMC_SREF_REQ_OFFSET  0

#define DMC_DFI_INIT_START_LEN    1
#define DMC_DFI_INIT_START_OFFSET 1
#define DMC_INIT_REQ_LEN          1
#define DMC_INIT_REQ_OFFSET       0

#define DMC_DDR3_RST_N_LEN    1
#define DMC_DDR3_RST_N_OFFSET 0

#define DMC_CMD_REQ_LEN    1
#define DMC_CMD_REQ_OFFSET 0

#define DMC_PERF_EVENT_ENABLE_LEN    1
#define DMC_PERF_EVENT_ENABLE_OFFSET 1
#define DMC_PERF_EN_LEN              1
#define DMC_PERF_EN_OFFSET           0

#define DMC_MTEST_START_LEN    1
#define DMC_MTEST_START_OFFSET 0

#define DMC_MCLR_START_LEN    1
#define DMC_MCLR_START_OFFSET 0

#define DMC_SYS_LP_CNT_LEN    12
#define DMC_SYS_LP_CNT_OFFSET 20
#define DMC_T_WCKE_LEN        4
#define DMC_T_WCKE_OFFSET     16
#define DMC_TLP_RESP_LEN      4
#define DMC_TLP_RESP_OFFSET   12
#define DMC_TLP_WAKEUP_LEN    4
#define DMC_TLP_WAKEUP_OFFSET 8
#define DMC_LP_ACK_LEN        1
#define DMC_LP_ACK_OFFSET     5
#define DMC_LP_SOFT_EN_LEN    1
#define DMC_LP_SOFT_EN_OFFSET 4
#define DMC_SYS_GT_EN_LEN     1
#define DMC_SYS_GT_EN_OFFSET  1
#define DMC_LP_EN_LEN         1
#define DMC_LP_EN_OFFSET      0

#define DMC_SREF_AREFNUM_LEN         4
#define DMC_SREF_AREFNUM_OFFSET      12
#define DMC_CLK_SWITCH_LEN           1
#define DMC_CLK_SWITCH_OFFSET        8
#define DMC_SREF_FLUSH_EN_LEN        1
#define DMC_SREF_FLUSH_EN_OFFSET     5
#define DMC_SREF_ODIS_LEN            1
#define DMC_SREF_ODIS_OFFSET         4
#define DMC_INIT_XSREF_LEN           1
#define DMC_INIT_XSREF_OFFSET        3
#define DMC_SREF_PD_LEN              1
#define DMC_SREF_PD_OFFSET           2
#define DMC_ASREF_FAST_WAKEUP_LEN    1
#define DMC_ASREF_FAST_WAKEUP_OFFSET 1
#define DMC_SREF_CC_LEN              1
#define DMC_SREF_CC_OFFSET           0

#define DMC_WRLVL_EN_LEN        1
#define DMC_WRLVL_EN_OFFSET     8
#define DMC_INIT_AREFNUM_LEN    8
#define DMC_INIT_AREFNUM_OFFSET 0

#define DMC_ASREF_PRD_LEN    12
#define DMC_ASREF_PRD_OFFSET 20
#define DMC_T_CLK_CKE_LEN    4
#define DMC_T_CLK_CKE_OFFSET 16
#define DMC_PD_PRD_LEN       12
#define DMC_PD_PRD_OFFSET    4
#define DMC_PD_CC_LEN        1
#define DMC_PD_CC_OFFSET     2
#define DMC_PD_AC_LEN        1
#define DMC_PD_AC_OFFSET     1
#define DMC_PD_EN_LEN        1
#define DMC_PD_EN_OFFSET     0

#define DMC_RF_RATE_CTRL_LEN      5
#define DMC_RF_RATE_CTRL_OFFSET   24
#define DMC_AREF_COMP_LEN         1
#define DMC_AREF_COMP_OFFSET      23
#define DMC_AREF_CH_MODE_LEN      1
#define DMC_AREF_CH_MODE_OFFSET   22
#define DMC_MODIFIED_MODE_LEN     1
#define DMC_MODIFIED_MODE_OFFSET  20
#define DMC_PHYUPD_LEVEL_LEN      3
#define DMC_PHYUPD_LEVEL_OFFSET   16
#define DMC_AREF_ALARM_NUM_LEN    8
#define DMC_AREF_ALARM_NUM_OFFSET 8
#define DMC_PSTPND_LEVEL_LEN      3
#define DMC_PSTPND_LEVEL_OFFSET   5
#define DMC_AREF_ALARM_EN_LEN     1
#define DMC_AREF_ALARM_EN_OFFSET  4
#define DMC_AREF_DUAL_RANK_LEN    1
#define DMC_AREF_DUAL_RANK_OFFSET 3
#define DMC_AREF_OPT_LEN          1
#define DMC_AREF_OPT_OFFSET       2

#define DMC_ECC_MSK_LEN     1
#define DMC_ECC_MSK_OFFSET  9
#define DMC_ECC_BYP_LEN     1
#define DMC_ECC_BYP_OFFSET  8
#define DMC_ECCWB_EN_LEN    1
#define DMC_ECCWB_EN_OFFSET 4
#define DMC_ECC_EN_LEN      1
#define DMC_ECC_EN_OFFSET   0

#define DMC_ERR_INJECT_MASK_LEN    16
#define DMC_ERR_INJECT_MASK_OFFSET 16
#define DMC_ERR_INJECT_BL1_LEN     5
#define DMC_ERR_INJECT_BL1_OFFSET  9
#define DMC_ERR_INJECT_BL0_LEN     5
#define DMC_ERR_INJECT_BL0_OFFSET  4
#define DMC_ERR_INJECT_MODE_LEN    2
#define DMC_ERR_INJECT_MODE_OFFSET 0

#define DMC_RECRAM_ERR_INJ_LEN    2
#define DMC_RECRAM_ERR_INJ_OFFSET 8
#define DMC_RPRAM_ERR_INJ_LEN     2
#define DMC_RPRAM_ERR_INJ_OFFSET  4
#define DMC_WSRAM_ERR_INJ_LEN     2
#define DMC_WSRAM_ERR_INJ_OFFSET  2
#define DMC_SBRAM_ERR_INJ_LEN     2
#define DMC_SBRAM_ERR_INJ_OFFSET  0

#define DMC_OP_SWITCH_LEN    1
#define DMC_OP_SWITCH_OFFSET 0

#define DMC_WR_RCV_MODE_LEN       1
#define DMC_WR_RCV_MODE_OFFSET    28
#define DMC_EXCLU_EN_LEN          1
#define DMC_EXCLU_EN_OFFSET       24
#define DMC_REORDER_EN_LEN        1
#define DMC_REORDER_EN_OFFSET     20
#define DMC_QOS_MODE_LEN          1
#define DMC_QOS_MODE_OFFSET       16
#define DMC_MID_PUSH_EN_LEN       1
#define DMC_MID_PUSH_EN_OFFSET    15
#define DMC_WR_INTLV_EN_LEN       1
#define DMC_WR_INTLV_EN_OFFSET    14
#define DMC_RAM_PD_EN_LEN         1
#define DMC_RAM_PD_EN_OFFSET      13
#define DMC_READ_MODE_LEN         1
#define DMC_READ_MODE_OFFSET      12
#define DMC_ADDR_MODE_LEN         2
#define DMC_ADDR_MODE_OFFSET      10
#define DMC_INTLV_EN_LEN          1
#define DMC_INTLV_EN_OFFSET       9
#define DMC_WRAP_EN_LEN           1
#define DMC_WRAP_EN_OFFSET        8
#define DMC_GLOBAL_CLKON_LEN      1
#define DMC_GLOBAL_CLKON_OFFSET   6
#define DMC_EXMBIST_CLKON_LEN     1
#define DMC_EXMBIST_CLKON_OFFSET  5
#define DMC_APRE_EN_LEN           1
#define DMC_APRE_EN_OFFSET        4
#define DMC_FUNC_CLKON_LEN        1
#define DMC_FUNC_CLKON_OFFSET     3
#define DMC_DATA_CLKON_LEN        1
#define DMC_DATA_CLKON_OFFSET     2
#define DMC_CMD_CLKON_LEN         1
#define DMC_CMD_CLKON_OFFSET      1
#define DMC_OSC_RETRAIN_EN_LEN    1
#define DMC_OSC_RETRAIN_EN_OFFSET 0

#define DMC_OPENPAGE_TIME_LEN    14
#define DMC_OPENPAGE_TIME_OFFSET 16
#define DMC_RANK_DISABLE_LEN     16
#define DMC_RANK_DISABLE_OFFSET  0

#define DMC_TRDCSLAT_LEN    4
#define DMC_TRDCSLAT_OFFSET 16
#define DMC_TWRCSLAT_LEN    4
#define DMC_TWRCSLAT_OFFSET 12
#define DMC_TCAL_LEN        4
#define DMC_TCAL_OFFSET     8
#define DMC_TPL_LEN         4
#define DMC_TPL_OFFSET      4
#define DMC_TDBI_LEN        4
#define DMC_TDBI_OFFSET     0

#define DMC_BANK_MODE_LEN       4
#define DMC_BANK_MODE_OFFSET    28
#define DMC_BANK_XOR_LEN        3
#define DMC_BANK_XOR_OFFSET     24
#define DMC_ASREF_ZQC_EN_LEN    1
#define DMC_ASREF_ZQC_EN_OFFSET 23
#define DMC_SREF_ZQC_EN_LEN     1
#define DMC_SREF_ZQC_EN_OFFSET  22
#define DMC_RANK_LEN            2
#define DMC_RANK_OFFSET         20
#define DMC_RANK_MODE_LEN       2
#define DMC_RANK_MODE_OFFSET    18
#define DMC_ODT_ON_LEN          1
#define DMC_ODT_ON_OFFSET       17
#define DMC_ZQC_EN_LEN          1
#define DMC_ZQC_EN_OFFSET       16
#define DMC_CRC_EN_LEN          1
#define DMC_CRC_EN_OFFSET       15
#define DMC_SCRAMB_EN_LEN       1
#define DMC_SCRAMB_EN_OFFSET    14
#define DMC_BC_EN_LEN           1
#define DMC_BC_EN_OFFSET        12
#define DMC_CMD_2T_EN_LEN       1
#define DMC_CMD_2T_EN_OFFSET    11
#define DMC_WR_3T_PRE_LEN       1
#define DMC_WR_3T_PRE_OFFSET    10
#define DMC_WR_2T_PRE_LEN       1
#define DMC_WR_2T_PRE_OFFSET    9
#define DMC_ZQ_CH_MODE_LEN      1
#define DMC_ZQ_CH_MODE_OFFSET   8
#define DMC_MEM_WIDTH_LEN       2
#define DMC_MEM_WIDTH_OFFSET    4
#define DMC_DRAM_TYPE_LEN       4
#define DMC_DRAM_TYPE_OFFSET    0

#define DMC_PAR_DLY_LEN          1
#define DMC_PAR_DLY_OFFSET       12
#define DMC_CKE_SHARE_MAP_LEN    2
#define DMC_CKE_SHARE_MAP_OFFSET 8
#define DMC_PARITY_EN_LEN        1
#define DMC_PARITY_EN_OFFSET     4
#define DMC_ADDR_MIRROR_LEN      1
#define DMC_ADDR_MIRROR_OFFSET   0

#define DMC_MRR_DBI_BYP_LEN         1
#define DMC_MRR_DBI_BYP_OFFSET      19
#define DMC_DBI_LOW_ACT_LEN         1
#define DMC_DBI_LOW_ACT_OFFSET      18
#define DMC_DMI_PATTERN_LEN         8
#define DMC_DMI_PATTERN_OFFSET      8
#define DMC_SCRAMB_SEED_TYPE_LEN    1
#define DMC_SCRAMB_SEED_TYPE_OFFSET 4
#define DMC_SCRAMB_SEED_SORT_LEN    3
#define DMC_SCRAMB_SEED_SORT_OFFSET 0

#define DMC_MEM_X4_0_LEN           1
#define DMC_MEM_X4_0_OFFSET        16
#define DMC_MEM_MAP_0_LEN          2
#define DMC_MEM_MAP_0_OFFSET       12
#define DMC_MEM_BANKGROUP_0_LEN    2
#define DMC_MEM_BANKGROUP_0_OFFSET 10
#define DMC_MEM_BANK_0_LEN         2
#define DMC_MEM_BANK_0_OFFSET      8
#define DMC_MEM_ROW_0_LEN          3
#define DMC_MEM_ROW_0_OFFSET       4
#define DMC_MEM_COL_0_LEN          3
#define DMC_MEM_COL_0_OFFSET       0

#define DMC_MEM_X4_1_LEN           1
#define DMC_MEM_X4_1_OFFSET        16
#define DMC_MEM_MAP_1_LEN          2
#define DMC_MEM_MAP_1_OFFSET       12
#define DMC_MEM_BANKGROUP_1_LEN    2
#define DMC_MEM_BANKGROUP_1_OFFSET 10
#define DMC_MEM_BANK_1_LEN         2
#define DMC_MEM_BANK_1_OFFSET      8
#define DMC_MEM_ROW_1_LEN          3
#define DMC_MEM_ROW_1_OFFSET       4
#define DMC_MEM_COL_1_LEN          3
#define DMC_MEM_COL_1_OFFSET       0

#define DMC_MEM_X4_2_LEN           1
#define DMC_MEM_X4_2_OFFSET        16
#define DMC_MEM_MAP_2_LEN          2
#define DMC_MEM_MAP_2_OFFSET       12
#define DMC_MEM_BANKGROUP_2_LEN    2
#define DMC_MEM_BANKGROUP_2_OFFSET 10
#define DMC_MEM_BANK_2_LEN         2
#define DMC_MEM_BANK_2_OFFSET      8
#define DMC_MEM_ROW_2_LEN          3
#define DMC_MEM_ROW_2_OFFSET       4
#define DMC_MEM_COL_2_LEN          3
#define DMC_MEM_COL_2_OFFSET       0

#define DMC_MEM_X4_3_LEN           1
#define DMC_MEM_X4_3_OFFSET        16
#define DMC_MEM_MAP_3_LEN          2
#define DMC_MEM_MAP_3_OFFSET       12
#define DMC_MEM_BANKGROUP_3_LEN    2
#define DMC_MEM_BANKGROUP_3_OFFSET 10
#define DMC_MEM_BANK_3_LEN         2
#define DMC_MEM_BANK_3_OFFSET      8
#define DMC_MEM_ROW_3_LEN          3
#define DMC_MEM_ROW_3_OFFSET       4
#define DMC_MEM_COL_3_LEN          3
#define DMC_MEM_COL_3_OFFSET       0

#define DMC_MEM_X4_4_LEN           1
#define DMC_MEM_X4_4_OFFSET        16
#define DMC_MEM_MAP_4_LEN          2
#define DMC_MEM_MAP_4_OFFSET       12
#define DMC_MEM_BANKGROUP_4_LEN    2
#define DMC_MEM_BANKGROUP_4_OFFSET 10
#define DMC_MEM_BANK_4_LEN         2
#define DMC_MEM_BANK_4_OFFSET      8
#define DMC_MEM_ROW_4_LEN          3
#define DMC_MEM_ROW_4_OFFSET       4
#define DMC_MEM_COL_4_LEN          3
#define DMC_MEM_COL_4_OFFSET       0

#define DMC_MEM_X4_5_LEN           1
#define DMC_MEM_X4_5_OFFSET        16
#define DMC_MEM_MAP_5_LEN          2
#define DMC_MEM_MAP_5_OFFSET       12
#define DMC_MEM_BANKGROUP_5_LEN    2
#define DMC_MEM_BANKGROUP_5_OFFSET 10
#define DMC_MEM_BANK_5_LEN         2
#define DMC_MEM_BANK_5_OFFSET      8
#define DMC_MEM_ROW_5_LEN          3
#define DMC_MEM_ROW_5_OFFSET       4
#define DMC_MEM_COL_5_LEN          3
#define DMC_MEM_COL_5_OFFSET       0

#define DMC_MEM_X4_6_LEN           1
#define DMC_MEM_X4_6_OFFSET        16
#define DMC_MEM_MAP_6_LEN          2
#define DMC_MEM_MAP_6_OFFSET       12
#define DMC_MEM_BANKGROUP_6_LEN    2
#define DMC_MEM_BANKGROUP_6_OFFSET 10
#define DMC_MEM_BANK_6_LEN         2
#define DMC_MEM_BANK_6_OFFSET      8
#define DMC_MEM_ROW_6_LEN          3
#define DMC_MEM_ROW_6_OFFSET       4
#define DMC_MEM_COL_6_LEN          3
#define DMC_MEM_COL_6_OFFSET       0

#define DMC_MEM_X4_7_LEN           1
#define DMC_MEM_X4_7_OFFSET        16
#define DMC_MEM_MAP_7_LEN          2
#define DMC_MEM_MAP_7_OFFSET       12
#define DMC_MEM_BANKGROUP_7_LEN    2
#define DMC_MEM_BANKGROUP_7_OFFSET 10
#define DMC_MEM_BANK_7_LEN         2
#define DMC_MEM_BANK_7_OFFSET      8
#define DMC_MEM_ROW_7_LEN          3
#define DMC_MEM_ROW_7_OFFSET       4
#define DMC_MEM_COL_7_LEN          3
#define DMC_MEM_COL_7_OFFSET       0

#define DMC_MEM_X4_8_LEN           1
#define DMC_MEM_X4_8_OFFSET        16
#define DMC_MEM_MAP_8_LEN          2
#define DMC_MEM_MAP_8_OFFSET       12
#define DMC_MEM_BANKGROUP_8_LEN    2
#define DMC_MEM_BANKGROUP_8_OFFSET 10
#define DMC_MEM_BANK_8_LEN         2
#define DMC_MEM_BANK_8_OFFSET      8
#define DMC_MEM_ROW_8_LEN          3
#define DMC_MEM_ROW_8_OFFSET       4
#define DMC_MEM_COL_8_LEN          3
#define DMC_MEM_COL_8_OFFSET       0

#define DMC_MEM_X4_9_LEN           1
#define DMC_MEM_X4_9_OFFSET        16
#define DMC_MEM_MAP_9_LEN          2
#define DMC_MEM_MAP_9_OFFSET       12
#define DMC_MEM_BANKGROUP_9_LEN    2
#define DMC_MEM_BANKGROUP_9_OFFSET 10
#define DMC_MEM_BANK_9_LEN         2
#define DMC_MEM_BANK_9_OFFSET      8
#define DMC_MEM_ROW_9_LEN          3
#define DMC_MEM_ROW_9_OFFSET       4
#define DMC_MEM_COL_9_LEN          3
#define DMC_MEM_COL_9_OFFSET       0

#define DMC_MEM_X4_10_LEN           1
#define DMC_MEM_X4_10_OFFSET        16
#define DMC_MEM_MAP_10_LEN          2
#define DMC_MEM_MAP_10_OFFSET       12
#define DMC_MEM_BANKGROUP_10_LEN    2
#define DMC_MEM_BANKGROUP_10_OFFSET 10
#define DMC_MEM_BANK_10_LEN         2
#define DMC_MEM_BANK_10_OFFSET      8
#define DMC_MEM_ROW_10_LEN          3
#define DMC_MEM_ROW_10_OFFSET       4
#define DMC_MEM_COL_10_LEN          3
#define DMC_MEM_COL_10_OFFSET       0

#define DMC_MEM_X4_11_LEN           1
#define DMC_MEM_X4_11_OFFSET        16
#define DMC_MEM_MAP_11_LEN          2
#define DMC_MEM_MAP_11_OFFSET       12
#define DMC_MEM_BANKGROUP_11_LEN    2
#define DMC_MEM_BANKGROUP_11_OFFSET 10
#define DMC_MEM_BANK_11_LEN         2
#define DMC_MEM_BANK_11_OFFSET      8
#define DMC_MEM_ROW_11_LEN          3
#define DMC_MEM_ROW_11_OFFSET       4
#define DMC_MEM_COL_11_LEN          3
#define DMC_MEM_COL_11_OFFSET       0

#define DMC_MEM_X4_12_LEN           1
#define DMC_MEM_X4_12_OFFSET        16
#define DMC_MEM_MAP_12_LEN          2
#define DMC_MEM_MAP_12_OFFSET       12
#define DMC_MEM_BANKGROUP_12_LEN    2
#define DMC_MEM_BANKGROUP_12_OFFSET 10
#define DMC_MEM_BANK_12_LEN         2
#define DMC_MEM_BANK_12_OFFSET      8
#define DMC_MEM_ROW_12_LEN          3
#define DMC_MEM_ROW_12_OFFSET       4
#define DMC_MEM_COL_12_LEN          3
#define DMC_MEM_COL_12_OFFSET       0

#define DMC_MEM_X4_13_LEN           1
#define DMC_MEM_X4_13_OFFSET        16
#define DMC_MEM_MAP_13_LEN          2
#define DMC_MEM_MAP_13_OFFSET       12
#define DMC_MEM_BANKGROUP_13_LEN    2
#define DMC_MEM_BANKGROUP_13_OFFSET 10
#define DMC_MEM_BANK_13_LEN         2
#define DMC_MEM_BANK_13_OFFSET      8
#define DMC_MEM_ROW_13_LEN          3
#define DMC_MEM_ROW_13_OFFSET       4
#define DMC_MEM_COL_13_LEN          3
#define DMC_MEM_COL_13_OFFSET       0

#define DMC_MEM_X4_14_LEN           1
#define DMC_MEM_X4_14_OFFSET        16
#define DMC_MEM_MAP_14_LEN          2
#define DMC_MEM_MAP_14_OFFSET       12
#define DMC_MEM_BANKGROUP_14_LEN    2
#define DMC_MEM_BANKGROUP_14_OFFSET 10
#define DMC_MEM_BANK_14_LEN         2
#define DMC_MEM_BANK_14_OFFSET      8
#define DMC_MEM_ROW_14_LEN          3
#define DMC_MEM_ROW_14_OFFSET       4
#define DMC_MEM_COL_14_LEN          3
#define DMC_MEM_COL_14_OFFSET       0

#define DMC_MEM_X4_15_LEN           1
#define DMC_MEM_X4_15_OFFSET        16
#define DMC_MEM_MAP_15_LEN          2
#define DMC_MEM_MAP_15_OFFSET       12
#define DMC_MEM_BANKGROUP_15_LEN    2
#define DMC_MEM_BANKGROUP_15_OFFSET 10
#define DMC_MEM_BANK_15_LEN         2
#define DMC_MEM_BANK_15_OFFSET      8
#define DMC_MEM_ROW_15_LEN          3
#define DMC_MEM_ROW_15_OFFSET       4
#define DMC_MEM_COL_15_LEN          3
#define DMC_MEM_COL_15_OFFSET       0

#define DMC_RODT_0_LEN    16
#define DMC_RODT_0_OFFSET 16
#define DMC_WODT_0_LEN    16
#define DMC_WODT_0_OFFSET 0

#define DMC_RODT_1_LEN    16
#define DMC_RODT_1_OFFSET 16
#define DMC_WODT_1_LEN    16
#define DMC_WODT_1_OFFSET 0

#define DMC_RODT_2_LEN    16
#define DMC_RODT_2_OFFSET 16
#define DMC_WODT_2_LEN    16
#define DMC_WODT_2_OFFSET 0

#define DMC_RODT_3_LEN    16
#define DMC_RODT_3_OFFSET 16
#define DMC_WODT_3_LEN    16
#define DMC_WODT_3_OFFSET 0

#define DMC_RODT_4_LEN    16
#define DMC_RODT_4_OFFSET 16
#define DMC_WODT_4_LEN    16
#define DMC_WODT_4_OFFSET 0

#define DMC_RODT_5_LEN    16
#define DMC_RODT_5_OFFSET 16
#define DMC_WODT_5_LEN    16
#define DMC_WODT_5_OFFSET 0

#define DMC_RODT_6_LEN    16
#define DMC_RODT_6_OFFSET 16
#define DMC_WODT_6_LEN    16
#define DMC_WODT_6_OFFSET 0

#define DMC_RODT_7_LEN    16
#define DMC_RODT_7_OFFSET 16
#define DMC_WODT_7_LEN    16
#define DMC_WODT_7_OFFSET 0

#define DMC_RODT_8_LEN    16
#define DMC_RODT_8_OFFSET 16
#define DMC_WODT_8_LEN    16
#define DMC_WODT_8_OFFSET 0

#define DMC_RODT_9_LEN    16
#define DMC_RODT_9_OFFSET 16
#define DMC_WODT_9_LEN    16
#define DMC_WODT_9_OFFSET 0

#define DMC_RODT_10_LEN    16
#define DMC_RODT_10_OFFSET 16
#define DMC_WODT_10_LEN    16
#define DMC_WODT_10_OFFSET 0

#define DMC_RODT_11_LEN    16
#define DMC_RODT_11_OFFSET 16
#define DMC_WODT_11_LEN    16
#define DMC_WODT_11_OFFSET 0

#define DMC_RODT_12_LEN    16
#define DMC_RODT_12_OFFSET 16
#define DMC_WODT_12_LEN    16
#define DMC_WODT_12_OFFSET 0

#define DMC_RODT_13_LEN    16
#define DMC_RODT_13_OFFSET 16
#define DMC_WODT_13_LEN    16
#define DMC_WODT_13_OFFSET 0

#define DMC_RODT_14_LEN    16
#define DMC_RODT_14_OFFSET 16
#define DMC_WODT_14_LEN    16
#define DMC_WODT_14_OFFSET 0

#define DMC_RODT_15_LEN    16
#define DMC_RODT_15_OFFSET 16
#define DMC_WODT_15_LEN    16
#define DMC_WODT_15_OFFSET 0

#define DMC_CA_ODT_LEN    16
#define DMC_CA_ODT_OFFSET 0

#define DMC_WR_DBI_EN_LEN      1
#define DMC_WR_DBI_EN_OFFSET   8
#define DMC_RD_DBI_EN_LEN      1
#define DMC_RD_DBI_EN_OFFSET   7
#define DMC_RD_OTF_EN_LEN      1
#define DMC_RD_OTF_EN_OFFSET   6
#define DMC_WR_OTF_EN_LEN      1
#define DMC_WR_OTF_EN_OFFSET   5
#define DMC_LPDDR4_BL32_LEN    1
#define DMC_LPDDR4_BL32_OFFSET 4
#define DMC_BRSTLEN2_LEN       1
#define DMC_BRSTLEN2_OFFSET    3
#define DMC_BRSTLEN_LEN        1
#define DMC_BRSTLEN_OFFSET     2
#define DMC_CLK_RATIO2_LEN     1
#define DMC_CLK_RATIO2_OFFSET  1
#define DMC_CLK_RATIO_LEN      1
#define DMC_CLK_RATIO_OFFSET   0

#define DMC_WR_DBI_EN_LEN      1
#define DMC_WR_DBI_EN_OFFSET   8
#define DMC_RD_DBI_EN_LEN      1
#define DMC_RD_DBI_EN_OFFSET   7
#define DMC_RD_OTF_EN_LEN      1
#define DMC_RD_OTF_EN_OFFSET   6
#define DMC_WR_OTF_EN_LEN      1
#define DMC_WR_OTF_EN_OFFSET   5
#define DMC_LPDDR4_BL32_LEN    1
#define DMC_LPDDR4_BL32_OFFSET 4
#define DMC_BRSTLEN2_LEN       1
#define DMC_BRSTLEN2_OFFSET    3
#define DMC_BRSTLEN_LEN        1
#define DMC_BRSTLEN_OFFSET     2
#define DMC_CLK_RATIO2_LEN     1
#define DMC_CLK_RATIO2_OFFSET  1
#define DMC_CLK_RATIO_LEN      1
#define DMC_CLK_RATIO_OFFSET   0

#define DMC_TRTRRD_LEN     6
#define DMC_TRTRRD_OFFSET  16
#define DMC_TRAPMRW_LEN    6
#define DMC_TRAPMRW_OFFSET 8
#define DMC_TRMRW_LEN      6
#define DMC_TRMRW_OFFSET   0

#define DMC_TWRWTR_LEN     6
#define DMC_TWRWTR_OFFSET  16
#define DMC_TWAPMRW_LEN    6
#define DMC_TWAPMRW_OFFSET 8
#define DMC_TWMRW_LEN      6
#define DMC_TWMRW_OFFSET   0

#define DMC_TMRW_LEN      4
#define DMC_TMRW_OFFSET   28
#define DMC_TRRD_LEN      4
#define DMC_TRRD_OFFSET   24
#define DMC_TRP_PB_LEN    5
#define DMC_TRP_PB_OFFSET 19
#define DMC_TRCD_LEN      5
#define DMC_TRCD_OFFSET   14
#define DMC_TRC_LEN       7
#define DMC_TRC_OFFSET    7
#define DMC_TRAS_LEN      6
#define DMC_TRAS_OFFSET   0

#define DMC_TSRE_LEN     8
#define DMC_TSRE_OFFSET  24
#define DMC_TRTW_LEN     4
#define DMC_TRTW_OFFSET  20
#define DMC_TMRRI_LEN    5
#define DMC_TMRRI_OFFSET 14
#define DMC_TWL_LEN      6
#define DMC_TWL_OFFSET   8
#define DMC_TCL_LEN      6
#define DMC_TCL_OFFSET   0

#define DMC_TCKE_LEN      4
#define DMC_TCKE_OFFSET   28
#define DMC_TWTR_LEN      4
#define DMC_TWTR_OFFSET   24
#define DMC_TMPCWR_LEN    5
#define DMC_TMPCWR_OFFSET 18
#define DMC_TFAW_LEN      6
#define DMC_TFAW_OFFSET   12
#define DMC_TAREF_LEN     11
#define DMC_TAREF_OFFSET  0

#define DMC_TZQ_PRD_LEN    10
#define DMC_TZQ_PRD_OFFSET 22
#define DMC_TZQINIT_LEN    9
#define DMC_TZQINIT_OFFSET 13
#define DMC_TAOND_LEN      5
#define DMC_TAOND_OFFSET   8
#define DMC_TXARD_LEN      4
#define DMC_TXARD_OFFSET   4
#define DMC_TRTP_LEN       4
#define DMC_TRTP_OFFSET    0

#define DMC_TRODT_EXT_LEN    3
#define DMC_TRODT_EXT_OFFSET 28
#define DMC_TMRD_LEN         5
#define DMC_TMRD_OFFSET      20
#define DMC_TMRR_LEN         4
#define DMC_TMRR_OFFSET      16
#define DMC_TCCDMW32_LEN     6
#define DMC_TCCDMW32_OFFSET  8
#define DMC_TCCDMW16_LEN     6
#define DMC_TCCDMW16_OFFSET  0

#define DMC_TWODT_EXT_LEN    3
#define DMC_TWODT_EXT_OFFSET 28
#define DMC_TDQSCKMAX_LEN    3
#define DMC_TDQSCKMAX_OFFSET 24
#define DMC_TDQSCK_LEN       3
#define DMC_TDQSCK_OFFSET    20
#define DMC_TRNK2RNK_LEN     4
#define DMC_TRNK2RNK_OFFSET  16
#define DMC_TZQCS_LEN        8
#define DMC_TZQCS_OFFSET     8
#define DMC_TWR_LEN          5
#define DMC_TWR_OFFSET       0

#define DMC_TCCD_NSW_LEN    4
#define DMC_TCCD_NSW_OFFSET 28
#define DMC_TCCD_NSR_LEN    4
#define DMC_TCCD_NSR_OFFSET 24
#define DMC_TRRD_L_LEN      4
#define DMC_TRRD_L_OFFSET   20
#define DMC_TWTR_L_LEN      4
#define DMC_TWTR_L_OFFSET   16
#define DMC_TCCD_L_LEN      4
#define DMC_TCCD_L_OFFSET   12
#define DMC_TODT_SFT_LEN    4
#define DMC_TODT_SFT_OFFSET 8
#define DMC_TCKSRX_LEN      4
#define DMC_TCKSRX_OFFSET   4
#define DMC_TCKSRE_LEN      4
#define DMC_TCKSRE_OFFSET   0

#define DMC_TESCKE_LEN      4
#define DMC_TESCKE_OFFSET   28
#define DMC_TCKEHCMD_LEN    4
#define DMC_TCKEHCMD_OFFSET 24
#define DMC_TPBR2PBR_LEN    8
#define DMC_TPBR2PBR_OFFSET 16
#define DMC_RNK_TRTR_LEN    4
#define DMC_RNK_TRTR_OFFSET 12
#define DMC_RNK_TWTW_LEN    4
#define DMC_RNK_TWTW_OFFSET 8
#define DMC_RNK_TRTW_LEN    4
#define DMC_RNK_TRTW_OFFSET 4
#define DMC_RNK_TWTR_LEN    4
#define DMC_RNK_TWTR_OFFSET 0

#define DMC_TRFC_AB_LEN    9
#define DMC_TRFC_AB_OFFSET 19
#define DMC_TRFC_PB_LEN    9
#define DMC_TRFC_PB_OFFSET 10
#define DMC_TSR_LEN        5
#define DMC_TSR_OFFSET     5
#define DMC_TRP_AB_LEN     5
#define DMC_TRP_AB_OFFSET  0

#define DMC_TMRW_LEN      4
#define DMC_TMRW_OFFSET   28
#define DMC_TRRD_LEN      4
#define DMC_TRRD_OFFSET   24
#define DMC_TRP_PB_LEN    5
#define DMC_TRP_PB_OFFSET 19
#define DMC_TRCD_LEN      5
#define DMC_TRCD_OFFSET   14
#define DMC_TRC_LEN       7
#define DMC_TRC_OFFSET    7
#define DMC_TRAS_LEN      6
#define DMC_TRAS_OFFSET   0

#define DMC_TSRE_LEN     8
#define DMC_TSRE_OFFSET  24
#define DMC_TRTW_LEN     4
#define DMC_TRTW_OFFSET  20
#define DMC_TMRRI_LEN    5
#define DMC_TMRRI_OFFSET 14
#define DMC_TWL_LEN      6
#define DMC_TWL_OFFSET   8
#define DMC_TCL_LEN      6
#define DMC_TCL_OFFSET   0

#define DMC_TCKE_LEN      4
#define DMC_TCKE_OFFSET   28
#define DMC_TWTR_LEN      4
#define DMC_TWTR_OFFSET   24
#define DMC_TMPCWR_LEN    5
#define DMC_TMPCWR_OFFSET 18
#define DMC_TFAW_LEN      6
#define DMC_TFAW_OFFSET   12
#define DMC_TAREF_LEN     11
#define DMC_TAREF_OFFSET  0

#define DMC_TZQ_PRD_LEN    10
#define DMC_TZQ_PRD_OFFSET 22
#define DMC_TZQINIT_LEN    9
#define DMC_TZQINIT_OFFSET 13
#define DMC_TAOND_LEN      5
#define DMC_TAOND_OFFSET   8
#define DMC_TXARD_LEN      4
#define DMC_TXARD_OFFSET   4
#define DMC_TRTP_LEN       4
#define DMC_TRTP_OFFSET    0

#define DMC_TRODT_EXT_LEN    3
#define DMC_TRODT_EXT_OFFSET 28
#define DMC_TMRD_LEN         5
#define DMC_TMRD_OFFSET      20
#define DMC_TMRR_LEN         4
#define DMC_TMRR_OFFSET      16
#define DMC_TCCDMW32_LEN     6
#define DMC_TCCDMW32_OFFSET  8
#define DMC_TCCDMW16_LEN     6
#define DMC_TCCDMW16_OFFSET  0

#define DMC_TWODT_EXT_LEN    3
#define DMC_TWODT_EXT_OFFSET 28
#define DMC_TDQSCKMAX_LEN    3
#define DMC_TDQSCKMAX_OFFSET 24
#define DMC_TDQSCK_LEN       3
#define DMC_TDQSCK_OFFSET    20
#define DMC_TRNK2RNK_LEN     4
#define DMC_TRNK2RNK_OFFSET  16
#define DMC_TZQCS_LEN        8
#define DMC_TZQCS_OFFSET     8
#define DMC_TWR_LEN          5
#define DMC_TWR_OFFSET       0

#define DMC_TCCD_NSW_LEN    4
#define DMC_TCCD_NSW_OFFSET 28
#define DMC_TCCD_NSR_LEN    4
#define DMC_TCCD_NSR_OFFSET 24
#define DMC_TRRD_L_LEN      4
#define DMC_TRRD_L_OFFSET   20
#define DMC_TWTR_L_LEN      4
#define DMC_TWTR_L_OFFSET   16
#define DMC_TCCD_L_LEN      4
#define DMC_TCCD_L_OFFSET   12
#define DMC_TODT_SFT_LEN    4
#define DMC_TODT_SFT_OFFSET 8
#define DMC_TCKSRX_LEN      4
#define DMC_TCKSRX_OFFSET   4
#define DMC_TCKSRE_LEN      4
#define DMC_TCKSRE_OFFSET   0

#define DMC_TESCKE_LEN      4
#define DMC_TESCKE_OFFSET   28
#define DMC_TCKEHCMD_LEN    4
#define DMC_TCKEHCMD_OFFSET 24
#define DMC_TPBR2PBR_LEN    8
#define DMC_TPBR2PBR_OFFSET 16
#define DMC_RNK_TRTR_LEN    4
#define DMC_RNK_TRTR_OFFSET 12
#define DMC_RNK_TWTW_LEN    4
#define DMC_RNK_TWTW_OFFSET 8
#define DMC_RNK_TRTW_LEN    4
#define DMC_RNK_TRTW_OFFSET 4
#define DMC_RNK_TWTR_LEN    4
#define DMC_RNK_TWTR_OFFSET 0

#define DMC_TRFC_AB_LEN    9
#define DMC_TRFC_AB_OFFSET 19
#define DMC_TRFC_PB_LEN    9
#define DMC_TRFC_PB_OFFSET 10
#define DMC_TSR_LEN        5
#define DMC_TSR_OFFSET     5
#define DMC_TRP_AB_LEN     5
#define DMC_TRP_AB_OFFSET  0

#define DMC_BL_DATA_LEN    4
#define DMC_BL_DATA_OFFSET 0

#define DMC_MBIST_QUE_LEVEL_LEN    5
#define DMC_MBIST_QUE_LEVEL_OFFSET 8
#define DMC_QUE_LEVEL_LEN          5
#define DMC_QUE_LEVEL_OFFSET       0

#define DMC_HIQOS_RW_EN_LEN     1
#define DMC_HIQOS_RW_EN_OFFSET  1
#define DMC_HIQOS_PRE_EN_LEN    1
#define DMC_HIQOS_PRE_EN_OFFSET 0

#define DMC_PRIADPT_LEN    4
#define DMC_PRIADPT_OFFSET 4
#define DMC_AGEPRD_LEN     4
#define DMC_AGEPRD_OFFSET  0

#define DMC_EXMBIST_CMD_LEN    32
#define DMC_EXMBIST_CMD_OFFSET 0

#define DMC_EXMBIST_DIN_LEN    32
#define DMC_EXMBIST_DIN_OFFSET 0

#define DMC_MBIST_RANK_LEN        4
#define DMC_MBIST_RANK_OFFSET     28
#define DMC_MBIST_TOP_ADDR_LEN    28
#define DMC_MBIST_TOP_ADDR_OFFSET 0

#define DMC_MCLR_PATTERN0_LEN    32
#define DMC_MCLR_PATTERN0_OFFSET 0

#define DMC_MCLR_PATTERN1_LEN    32
#define DMC_MCLR_PATTERN1_OFFSET 0

#define DMC_MCLR_PATTERN2_LEN    32
#define DMC_MCLR_PATTERN2_OFFSET 0

#define DMC_MCLR_PATTERN3_LEN    32
#define DMC_MCLR_PATTERN3_OFFSET 0

#define DMC_MCLR_PATTERN4_LEN    32
#define DMC_MCLR_PATTERN4_OFFSET 0

#define DMC_OSC_PRD_LEN    28
#define DMC_OSC_PRD_OFFSET 0

#define DMC_OSC_THRESHOLD_LEN    16
#define DMC_OSC_THRESHOLD_OFFSET 16
#define DMC_OSC_RUN_TIME_LEN     16
#define DMC_OSC_RUN_TIME_OFFSET  0

#define DMC_TRAIN_EN_LEN    1
#define DMC_TRAIN_EN_OFFSET 0

#define DMC_PHYIF_TIM_WDEN_LEN    8
#define DMC_PHYIF_TIM_WDEN_OFFSET 24
#define DMC_PHYIF_TIM_RODT_LEN    8
#define DMC_PHYIF_TIM_RODT_OFFSET 16
#define DMC_PHYIF_TIM_WODT_LEN    8
#define DMC_PHYIF_TIM_WODT_OFFSET 8
#define DMC_PHYIF_TIM_OVEN_LEN    7
#define DMC_PHYIF_TIM_OVEN_OFFSET 0

#define DMC_PHYIF_TIM_RDCS_LEN    8
#define DMC_PHYIF_TIM_RDCS_OFFSET 24
#define DMC_PHYIF_TIM_RDEN_LEN    8
#define DMC_PHYIF_TIM_RDEN_OFFSET 16
#define DMC_PHYIF_TIM_WDDA_LEN    8
#define DMC_PHYIF_TIM_WDDA_OFFSET 8
#define DMC_PHYIF_TIM_WDCS_LEN    8
#define DMC_PHYIF_TIM_WDCS_OFFSET 0

#define DMC_PSTPD_PRD_LEN    8
#define DMC_PSTPD_PRD_OFFSET 16
#define DMC_PREPD_PRD_LEN    16
#define DMC_PREPD_PRD_OFFSET 0

#define DMC_CRC_LIMINAL_LEN    6
#define DMC_CRC_LIMINAL_OFFSET 12
#define DMC_REC_MAX_NUM_LEN    4
#define DMC_REC_MAX_NUM_OFFSET 8
#define DMC_REC_REF_NUM_LEN    4
#define DMC_REC_REF_NUM_OFFSET 4
#define DMC_REC_UPD_EN_LEN     1
#define DMC_REC_UPD_EN_OFFSET  2
#define DMC_REC_REF_EN_LEN     1
#define DMC_REC_REF_EN_OFFSET  1
#define DMC_REC_EN_LEN         1
#define DMC_REC_EN_OFFSET      0

#define DMC_TPHY2IO_DLY_LEN    5
#define DMC_TPHY2IO_DLY_OFFSET 25
#define DMC_TCRC_ALERT_LEN     5
#define DMC_TCRC_ALERT_OFFSET  20
#define DMC_TPAR_ALERT_LEN     5
#define DMC_TPAR_ALERT_OFFSET  12
#define DMC_TIO2PHY_DLY_LEN    5
#define DMC_TIO2PHY_DLY_OFFSET 4
#define DMC_TALERT_SYN_LEN     4
#define DMC_TALERT_SYN_OFFSET  0

#define DMC_CRC_PIPE_BYPASS_LEN    1
#define DMC_CRC_PIPE_BYPASS_OFFSET 20
#define DMC_DEVICE_X8_X4_LEN       18
#define DMC_DEVICE_X8_X4_OFFSET    0

#define DMC_CRC_INJECT_NUM_LEN     5
#define DMC_CRC_INJECT_NUM_OFFSET  16
#define DMC_CRC_INJECT_PAT_LEN     8
#define DMC_CRC_INJECT_PAT_OFFSET  8
#define DMC_CRC_INJECT_DM_LEN      1
#define DMC_CRC_INJECT_DM_OFFSET   4
#define DMC_CRC_INJECT_MASK_LEN    1
#define DMC_CRC_INJECT_MASK_OFFSET 1
#define DMC_CRC_ERR_INJ_LEN        1
#define DMC_CRC_ERR_INJ_OFFSET     0

#define DMC_CRC_INJECT_BL_LEN       18
#define DMC_CRC_INJECT_BL_OFFSET    4
#define DMC_CRC_INJECT_BURST_LEN    4
#define DMC_CRC_INJECT_BURST_OFFSET 0

#define DMC_PAR_INJECT_CMD_LEN     8
#define DMC_PAR_INJECT_CMD_OFFSET  12
#define DMC_PAR_INJECT_NUM_LEN     5
#define DMC_PAR_INJECT_NUM_OFFSET  4
#define DMC_PAR_INJECT_MASK_LEN    1
#define DMC_PAR_INJECT_MASK_OFFSET 1
#define DMC_PAR_ERR_INJ_LEN        1
#define DMC_PAR_ERR_INJ_OFFSET     0

#define DMC_PAR_INJECT_POS_LEN    6
#define DMC_PAR_INJECT_POS_OFFSET 0

#define DMC_SOFT_BP_OK_LEN           1
#define DMC_SOFT_BP_OK_OFFSET        31
#define DMC_SOFT_BP_EN_LEN           1
#define DMC_SOFT_BP_EN_OFFSET        30
#define DMC_PHYUPD_N_PRE_TYPE_LEN    2
#define DMC_PHYUPD_N_PRE_TYPE_OFFSET 28
#define DMC_PHYUPD_N_PRE_LEN         1
#define DMC_PHYUPD_N_PRE_OFFSET      24
#define DMC_WR_BUSY_DLY_LEN          6
#define DMC_WR_BUSY_DLY_OFFSET       16
#define DMC_PHY_UPDEN_LEN            1
#define DMC_PHY_UPDEN_OFFSET         12
#define DMC_TRDLAT_LEN               4
#define DMC_TRDLAT_OFFSET            8
#define DMC_PHY_ZQEN_LEN             1
#define DMC_PHY_ZQEN_OFFSET          4
#define DMC_RCV_PDR_LEN              1
#define DMC_RCV_PDR_OFFSET           0

#define DMC_AGE_EN_LEN         1
#define DMC_AGE_EN_OFFSET      16
#define DMC_AGE_EXT_PRD_LEN    8
#define DMC_AGE_EXT_PRD_OFFSET 8
#define DMC_AGE_ENT_PRD_LEN    8
#define DMC_AGE_ENT_PRD_OFFSET 0

#define DMC_WAIT_RESERV_LEN    8
#define DMC_WAIT_RESERV_OFFSET 24
#define DMC_WAIT_TLAST_LEN     8
#define DMC_WAIT_TLAST_OFFSET  16
#define DMC_WAIT_TIME_LEN      6
#define DMC_WAIT_TIME_OFFSET   0

#define DMC_WAIT_EN_LEN          1
#define DMC_WAIT_EN_OFFSET       31
#define DMC_CMD_MRS_LEN          4
#define DMC_CMD_MRS_OFFSET       12
#define DMC_SFC_MSK_CTRL_LEN     1
#define DMC_SFC_MSK_CTRL_OFFSET  10
#define DMC_SFC_QUE_CLR_LEN      1
#define DMC_SFC_QUE_CLR_OFFSET   9
#define DMC_INFINITE_LOOP_LEN    1
#define DMC_INFINITE_LOOP_OFFSET 8
#define DMC_SFC_QUE_RPTR_LEN     8
#define DMC_SFC_QUE_RPTR_OFFSET  0

#define DMC_SFC_CMD_QUE_LEN    32
#define DMC_SFC_CMD_QUE_OFFSET 0

#define DMC_SFC_RANK_LEN    16
#define DMC_SFC_RANK_OFFSET 16

#define DMC_WDATA_LEN    32
#define DMC_WDATA_OFFSET 0

#define DMC_SFC_WDATA_PTR_LEN    32
#define DMC_SFC_WDATA_PTR_OFFSET 0

#define DMC_SFC_MASK0_LEN    32
#define DMC_SFC_MASK0_OFFSET 0

#define DMC_SFC_MASK1_LEN    32
#define DMC_SFC_MASK1_OFFSET 0

#define DMC_HIQOS_TIME3_LEN    8
#define DMC_HIQOS_TIME3_OFFSET 24
#define DMC_HIQOS_TIME2_LEN    8
#define DMC_HIQOS_TIME2_OFFSET 16
#define DMC_HIQOS_TIME1_LEN    8
#define DMC_HIQOS_TIME1_OFFSET 8
#define DMC_HIQOS_TIME0_LEN    8
#define DMC_HIQOS_TIME0_OFFSET 0

#define DMC_HIQOS_TIME7_LEN    8
#define DMC_HIQOS_TIME7_OFFSET 24
#define DMC_HIQOS_TIME6_LEN    8
#define DMC_HIQOS_TIME6_OFFSET 16
#define DMC_HIQOS_TIME5_LEN    8
#define DMC_HIQOS_TIME5_OFFSET 8
#define DMC_HIQOS_TIME4_LEN    8
#define DMC_HIQOS_TIME4_OFFSET 0

#define DMC_TMON_PRD_LEN    28
#define DMC_TMON_PRD_OFFSET 0

#define DMC_TMON_RANK_LEN    16
#define DMC_TMON_RANK_OFFSET 0

#define DMC_AREF_RATE_LEN    32
#define DMC_AREF_RATE_OFFSET 0

#define DMC_MRR_BYTE_LEN    5
#define DMC_MRR_BYTE_OFFSET 24
#define DMC_MRR_MAP_LEN     24
#define DMC_MRR_MAP_OFFSET  0

#define DMC_DAT_STAT_EN_LEN      1
#define DMC_DAT_STAT_EN_OFFSET   30
#define DMC_DAT_STAT_MODE_LEN    2
#define DMC_DAT_STAT_MODE_OFFSET 28
#define DMC_DAT_STAT_PRD_LEN     28
#define DMC_DAT_STAT_PRD_OFFSET  0

#define DMC_DMC_DAT_MIN_LEN    27
#define DMC_DMC_DAT_MIN_OFFSET 0

#define DMC_DMC_DAT_MAX_LEN    27
#define DMC_DMC_DAT_MAX_OFFSET 0

#define DMC_LOAD_STAT_EN_LEN      1
#define DMC_LOAD_STAT_EN_OFFSET   30
#define DMC_LOAD_STAT_MODE_LEN    2
#define DMC_LOAD_STAT_MODE_OFFSET 28
#define DMC_LOAD_STAT_PRD_LEN     28
#define DMC_LOAD_STAT_PRD_OFFSET  0

#define DMC_DMC_CMD_MIN_LEN    27
#define DMC_DMC_CMD_MIN_OFFSET 0

#define DMC_DMC_CMD_MAX_LEN    27
#define DMC_DMC_CMD_MAX_OFFSET 0

#define DMC_FLUX_EN_LEN      1
#define DMC_FLUX_EN_OFFSET   29
#define DMC_PERF_MODE_LEN    1
#define DMC_PERF_MODE_OFFSET 28
#define DMC_PERF_PRD_LEN     28
#define DMC_PERF_PRD_OFFSET  0

#define DMC_STA_ID_LEN    32
#define DMC_STA_ID_OFFSET 0

#define DMC_STA_IDMASK_LEN    32
#define DMC_STA_IDMASK_OFFSET 0

#define DMC_RET_MPC_CNT_LEN     3
#define DMC_RET_MPC_CNT_OFFSET  8
#define DMC_RET_CMD_TYPE_LEN    1
#define DMC_RET_CMD_TYPE_OFFSET 4
#define DMC_DUMMY_RD_EN_LEN     1
#define DMC_DUMMY_RD_EN_OFFSET  0

#define DMC_DUMMY_RD_MODE_LEN    2
#define DMC_DUMMY_RD_MODE_OFFSET 28
#define DMC_DUMMY_RD_CNT_LEN     28
#define DMC_DUMMY_RD_CNT_OFFSET  0

#define DMC_RPRAM_MERR_INT_MASK_LEN      1
#define DMC_RPRAM_MERR_INT_MASK_OFFSET   31
#define DMC_RECRAM_MERR_INT_MASK_LEN     1
#define DMC_RECRAM_MERR_INT_MASK_OFFSET  30
#define DMC_RECRAM_SERR_INT_MASK_LEN     1
#define DMC_RECRAM_SERR_INT_MASK_OFFSET  29
#define DMC_RPRAM_SERR_INT_MASK_LEN      1
#define DMC_RPRAM_SERR_INT_MASK_OFFSET   28
#define DMC_SBRAM_MERR_INT_MASK_LEN      1
#define DMC_SBRAM_MERR_INT_MASK_OFFSET   24
#define DMC_WSRAM_MERR_INT_MASK_LEN      1
#define DMC_WSRAM_MERR_INT_MASK_OFFSET   22
#define DMC_WSRAM_SERR_INT_MASK_LEN      1
#define DMC_WSRAM_SERR_INT_MASK_OFFSET   21
#define DMC_SBRAM_SERR_INT_MASK_LEN      1
#define DMC_SBRAM_SERR_INT_MASK_OFFSET   20
#define DMC_OSC_OVERFLOW_INT_MASK_LEN    1
#define DMC_OSC_OVERFLOW_INT_MASK_OFFSET 19
#define DMC_OSC_OVTH_INT_MASK_LEN        1
#define DMC_OSC_OVTH_INT_MASK_OFFSET     18
#define DMC_OSC_RD_INT_MASK_LEN          1
#define DMC_OSC_RD_INT_MASK_OFFSET       17
#define DMC_AREF_ALARM_INT_MASK_LEN      1
#define DMC_AREF_ALARM_INT_MASK_OFFSET   16
#define DMC_STADAT_MAX_INT_MASK_LEN      1
#define DMC_STADAT_MAX_INT_MASK_OFFSET   14
#define DMC_STADAT_MIN_INT_MASK_LEN      1
#define DMC_STADAT_MIN_INT_MASK_OFFSET   13
#define DMC_RDTIMEOUT_INT_MASK_LEN       1
#define DMC_RDTIMEOUT_INT_MASK_OFFSET    12
#define DMC_STACMD_MAX_INT_MASK_LEN      1
#define DMC_STACMD_MAX_INT_MASK_OFFSET   10
#define DMC_STACMD_MIN_INT_MASK_LEN      1
#define DMC_STACMD_MIN_INT_MASK_OFFSET   9
#define DMC_DIMM_PARITY_INT_MASK_LEN     1
#define DMC_DIMM_PARITY_INT_MASK_OFFSET  8
#define DMC_TMON_UPD_INT_MASK_LEN        1
#define DMC_TMON_UPD_INT_MASK_OFFSET     7
#define DMC_TMON_ERR_INT_MASK_LEN        1
#define DMC_TMON_ERR_INT_MASK_OFFSET     6
#define DMC_SREF_ERR_INT_MASK_LEN        1
#define DMC_SREF_ERR_INT_MASK_OFFSET     5
#define DMC_MERR_INT_MASK_LEN            1
#define DMC_MERR_INT_MASK_OFFSET         4
#define DMC_REC_ERR_INT_MASK_LEN         1
#define DMC_REC_ERR_INT_MASK_OFFSET      3
#define DMC_REC_INT_MASK_LEN             1
#define DMC_REC_INT_MASK_OFFSET          2
#define DMC_FLUX_INT_MASK_LEN            1
#define DMC_FLUX_INT_MASK_OFFSET         1
#define DMC_SERR_INT_MASK_LEN            1
#define DMC_SERR_INT_MASK_OFFSET         0

#define DMC_RPRAM_MERR_RINT_LEN      1
#define DMC_RPRAM_MERR_RINT_OFFSET   31
#define DMC_RECRAM_MERR_RINT_LEN     1
#define DMC_RECRAM_MERR_RINT_OFFSET  30
#define DMC_RECRAM_SERR_RINT_LEN     1
#define DMC_RECRAM_SERR_RINT_OFFSET  29
#define DMC_RPRAM_SERR_RINT_LEN      1
#define DMC_RPRAM_SERR_RINT_OFFSET   28
#define DMC_SBRAM_MERR_RINT_LEN      1
#define DMC_SBRAM_MERR_RINT_OFFSET   24
#define DMC_WSRAM_MERR_RINT_LEN      1
#define DMC_WSRAM_MERR_RINT_OFFSET   22
#define DMC_WSRAM_SERR_RINT_LEN      1
#define DMC_WSRAM_SERR_RINT_OFFSET   21
#define DMC_SBRAM_SERR_RINT_LEN      1
#define DMC_SBRAM_SERR_RINT_OFFSET   20
#define DMC_OSC_OVERFLOW_RINT_LEN    1
#define DMC_OSC_OVERFLOW_RINT_OFFSET 19
#define DMC_OSC_OVTH_RINT_LEN        1
#define DMC_OSC_OVTH_RINT_OFFSET     18
#define DMC_OSC_RD_RINT_LEN          1
#define DMC_OSC_RD_RINT_OFFSET       17
#define DMC_AREF_ALARM_RINT_LEN      1
#define DMC_AREF_ALARM_RINT_OFFSET   16
#define DMC_STADAT_MAX_RINT_LEN      1
#define DMC_STADAT_MAX_RINT_OFFSET   14
#define DMC_STADAT_MIN_RINT_LEN      1
#define DMC_STADAT_MIN_RINT_OFFSET   13
#define DMC_RDTIMEOUT_RINT_LEN       1
#define DMC_RDTIMEOUT_RINT_OFFSET    12
#define DMC_STACMD_MAX_RINT_LEN      1
#define DMC_STACMD_MAX_RINT_OFFSET   10
#define DMC_STACMD_MIN_RINT_LEN      1
#define DMC_STACMD_MIN_RINT_OFFSET   9
#define DMC_DIMM_PARITY_RINT_LEN     1
#define DMC_DIMM_PARITY_RINT_OFFSET  8
#define DMC_TMON_UPD_RINT_LEN        1
#define DMC_TMON_UPD_RINT_OFFSET     7
#define DMC_TMON_ERR_RINT_LEN        1
#define DMC_TMON_ERR_RINT_OFFSET     6
#define DMC_SREF_ERR_RINT_LEN        1
#define DMC_SREF_ERR_RINT_OFFSET     5
#define DMC_MERR_RINT_LEN            1
#define DMC_MERR_RINT_OFFSET         4
#define DMC_REC_ERR_RINT_LEN         1
#define DMC_REC_ERR_RINT_OFFSET      3
#define DMC_REC_RINT_LEN             1
#define DMC_REC_RINT_OFFSET          2
#define DMC_FLUX_RINT_LEN            1
#define DMC_FLUX_RINT_OFFSET         1
#define DMC_SERR_RINT_LEN            1
#define DMC_SERR_RINT_OFFSET         0

#define DMC_RPRAM_MERR_INTSTS_LEN      1
#define DMC_RPRAM_MERR_INTSTS_OFFSET   31
#define DMC_RECRAM_MERR_INTSTS_LEN     1
#define DMC_RECRAM_MERR_INTSTS_OFFSET  30
#define DMC_RECRAM_SERR_INTSTS_LEN     1
#define DMC_RECRAM_SERR_INTSTS_OFFSET  29
#define DMC_RPRAM_SERR_INTSTS_LEN      1
#define DMC_RPRAM_SERR_INTSTS_OFFSET   28
#define DMC_SBRAM_MERR_INTSTS_LEN      1
#define DMC_SBRAM_MERR_INTSTS_OFFSET   24
#define DMC_WSRAM_MERR_INTSTS_LEN      1
#define DMC_WSRAM_MERR_INTSTS_OFFSET   22
#define DMC_WSRAM_SERR_INTSTS_LEN      1
#define DMC_WSRAM_SERR_INTSTS_OFFSET   21
#define DMC_SBRAM_SERR_INTSTS_LEN      1
#define DMC_SBRAM_SERR_INTSTS_OFFSET   20
#define DMC_OSC_OVERFLOW_INTSTS_LEN    1
#define DMC_OSC_OVERFLOW_INTSTS_OFFSET 19
#define DMC_OSC_OVTH_INTSTS_LEN        1
#define DMC_OSC_OVTH_INTSTS_OFFSET     18
#define DMC_OSC_RD_INTSTS_LEN          1
#define DMC_OSC_RD_INTSTS_OFFSET       17
#define DMC_AREF_ALARM_INTSTS_LEN      1
#define DMC_AREF_ALARM_INTSTS_OFFSET   16
#define DMC_STADAT_MAX_INTSTS_LEN      1
#define DMC_STADAT_MAX_INTSTS_OFFSET   14
#define DMC_STADAT_MIN_INTSTS_LEN      1
#define DMC_STADAT_MIN_INTSTS_OFFSET   13
#define DMC_RDTIMEOUT_INTSTS_LEN       1
#define DMC_RDTIMEOUT_INTSTS_OFFSET    12
#define DMC_STACMD_MAX_INTSTS_LEN      1
#define DMC_STACMD_MAX_INTSTS_OFFSET   10
#define DMC_STACMD_MIN_INTSTS_LEN      1
#define DMC_STACMD_MIN_INTSTS_OFFSET   9
#define DMC_DIMM_PARITY_INTSTS_LEN     1
#define DMC_DIMM_PARITY_INTSTS_OFFSET  8
#define DMC_TMON_UPD_INTSTS_LEN        1
#define DMC_TMON_UPD_INTSTS_OFFSET     7
#define DMC_TMON_ERR_INTSTS_LEN        1
#define DMC_TMON_ERR_INTSTS_OFFSET     6
#define DMC_SREF_ERR_INTSTS_LEN        1
#define DMC_SREF_ERR_INTSTS_OFFSET     5
#define DMC_MERR_INTSTS_LEN            1
#define DMC_MERR_INTSTS_OFFSET         4
#define DMC_REC_ERR_INTSTS_LEN         1
#define DMC_REC_ERR_INTSTS_OFFSET      3
#define DMC_REC_INTSTS_LEN             1
#define DMC_REC_INTSTS_OFFSET          2
#define DMC_FLUX_INTSTS_LEN            1
#define DMC_FLUX_INTSTS_OFFSET         1
#define DMC_SERR_INTSTS_LEN            1
#define DMC_SERR_INTSTS_OFFSET         0

#define DMC_BUSY_FUNC_LEN    16
#define DMC_BUSY_FUNC_OFFSET 16
#define DMC_BUSY_DMC_LEN     1
#define DMC_BUSY_DMC_OFFSET  0

#define DMC_AREF_INTLV_MODE_STAT_LEN    1
#define DMC_AREF_INTLV_MODE_STAT_OFFSET 31
#define DMC_IN_RAM_PD_LEN               1
#define DMC_IN_RAM_PD_OFFSET            30
#define DMC_IN_SRPD_LEN                 1
#define DMC_IN_SRPD_OFFSET              29
#define DMC_IN_PHYUPD_LEN               1
#define DMC_IN_PHYUPD_OFFSET            28
#define DMC_IN_REC_LEN                  1
#define DMC_IN_REC_OFFSET               25
#define DMC_IN_MCLR_LEN                 1
#define DMC_IN_MCLR_OFFSET              24
#define DMC_IN_MTEST_LEN                1
#define DMC_IN_MTEST_OFFSET             20
#define DMC_IN_ECCWB_LEN                1
#define DMC_IN_ECCWB_OFFSET             16
#define DMC_IN_SFC_LEN                  1
#define DMC_IN_SFC_OFFSET               12
#define DMC_AREF_OPT_STAT_LEN           1
#define DMC_AREF_OPT_STAT_OFFSET        8
#define DMC_DFI_INIT_COMPLETE_LEN       1
#define DMC_DFI_INIT_COMPLETE_OFFSET    5
#define DMC_IN_INIT_LEN                 1
#define DMC_IN_INIT_OFFSET              4
#define DMC_IN_ZQ_LEN                   1
#define DMC_IN_ZQ_OFFSET                2
#define DMC_IN_SREF_LEN                 1
#define DMC_IN_SREF_OFFSET              0

#define DMC_IN_ASREF_LEN    16
#define DMC_IN_ASREF_OFFSET 16
#define DMC_IN_TMON_LEN     4
#define DMC_IN_TMON_OFFSET  4
#define DMC_IN_PD_LEN       4
#define DMC_IN_PD_OFFSET    0

#define DMC_IN_OSC_LEN         16
#define DMC_IN_OSC_OFFSET      16
#define DMC_IN_DUMMY_RD_LEN    16
#define DMC_IN_DUMMY_RD_OFFSET 0

#define DMC_DMC_CT_LEN    16
#define DMC_DMC_CT_OFFSET 16
#define DMC_DMC_CV_LEN    16
#define DMC_DMC_CV_OFFSET 0

#define DMC_WGNTFIFO_E_LEN    1
#define DMC_WGNTFIFO_E_OFFSET 0

#define DMC_ERR_BUF_SEL_LEN    1
#define DMC_ERR_BUF_SEL_OFFSET 0

#define DMC_SERR_ID_LEN    32
#define DMC_SERR_ID_OFFSET 0

#define DMC_SERR_ADR0_LEN    32
#define DMC_SERR_ADR0_OFFSET 0

#define DMC_SERR_ADR1_LEN    12
#define DMC_SERR_ADR1_OFFSET 0

#define DMC_SERR_RDATA0_LEN    32
#define DMC_SERR_RDATA0_OFFSET 0

#define DMC_SERR_RDATA1_LEN    32
#define DMC_SERR_RDATA1_OFFSET 0

#define DMC_SERR_RDATA2_LEN    32
#define DMC_SERR_RDATA2_OFFSET 0

#define DMC_SERR_RDATA3_LEN    32
#define DMC_SERR_RDATA3_OFFSET 0

#define DMC_SERR_RDATA4_LEN    32
#define DMC_SERR_RDATA4_OFFSET 0

#define DMC_SERR_RDATA5_LEN    32
#define DMC_SERR_RDATA5_OFFSET 0

#define DMC_SERR_RDATA6_LEN    32
#define DMC_SERR_RDATA6_OFFSET 0

#define DMC_SERR_RDATA7_LEN    32
#define DMC_SERR_RDATA7_OFFSET 0

#define DMC_SERR_RDATA8_LEN    32
#define DMC_SERR_RDATA8_OFFSET 0

#define DMC_SERR_EXPDATA0_LEN    32
#define DMC_SERR_EXPDATA0_OFFSET 0

#define DMC_SERR_EXPDATA1_LEN    32
#define DMC_SERR_EXPDATA1_OFFSET 0

#define DMC_SERR_EXPDATA2_LEN    32
#define DMC_SERR_EXPDATA2_OFFSET 0

#define DMC_SERR_EXPDATA3_LEN    32
#define DMC_SERR_EXPDATA3_OFFSET 0

#define DMC_SERR_EXPDATA4_LEN    32
#define DMC_SERR_EXPDATA4_OFFSET 0

#define DMC_SERR_EXPDATA5_LEN    32
#define DMC_SERR_EXPDATA5_OFFSET 0

#define DMC_SERR_EXPDATA6_LEN    32
#define DMC_SERR_EXPDATA6_OFFSET 0

#define DMC_SERR_EXPDATA7_LEN    32
#define DMC_SERR_EXPDATA7_OFFSET 0

#define DMC_SERR_EXPDATA8_LEN    32
#define DMC_SERR_EXPDATA8_OFFSET 0

#define DMC_MERR_ADR0_LEN    32
#define DMC_MERR_ADR0_OFFSET 0

#define DMC_MERR_ADR1_LEN    12
#define DMC_MERR_ADR1_OFFSET 0

#define DMC_MERR_ID_LEN    32
#define DMC_MERR_ID_OFFSET 0

#define DMC_MERR_RDATA0_LEN    32
#define DMC_MERR_RDATA0_OFFSET 0

#define DMC_MERR_RDATA1_LEN    32
#define DMC_MERR_RDATA1_OFFSET 0

#define DMC_MERR_RDATA2_LEN    32
#define DMC_MERR_RDATA2_OFFSET 0

#define DMC_MERR_RDATA3_LEN    32
#define DMC_MERR_RDATA3_OFFSET 0

#define DMC_MERR_RDATA4_LEN    32
#define DMC_MERR_RDATA4_OFFSET 0

#define DMC_MERR_RDATA5_LEN    32
#define DMC_MERR_RDATA5_OFFSET 0

#define DMC_MERR_RDATA6_LEN    32
#define DMC_MERR_RDATA6_OFFSET 0

#define DMC_MERR_RDATA7_LEN    32
#define DMC_MERR_RDATA7_OFFSET 0

#define DMC_MERR_RDATA8_LEN    32
#define DMC_MERR_RDATA8_OFFSET 0

#define DMC_MERR_EXPDATA0_LEN    32
#define DMC_MERR_EXPDATA0_OFFSET 0

#define DMC_MERR_EXPDATA1_LEN    32
#define DMC_MERR_EXPDATA1_OFFSET 0

#define DMC_MERR_EXPDATA2_LEN    32
#define DMC_MERR_EXPDATA2_OFFSET 0

#define DMC_MERR_EXPDATA3_LEN    32
#define DMC_MERR_EXPDATA3_OFFSET 0

#define DMC_MERR_EXPDATA4_LEN    32
#define DMC_MERR_EXPDATA4_OFFSET 0

#define DMC_MERR_EXPDATA5_LEN    32
#define DMC_MERR_EXPDATA5_OFFSET 0

#define DMC_MERR_EXPDATA6_LEN    32
#define DMC_MERR_EXPDATA6_OFFSET 0

#define DMC_MERR_EXPDATA7_LEN    32
#define DMC_MERR_EXPDATA7_OFFSET 0

#define DMC_MERR_EXPDATA8_LEN    32
#define DMC_MERR_EXPDATA8_OFFSET 0

#define DMC_SERR_CNT_LEN    32
#define DMC_SERR_CNT_OFFSET 0

#define DMC_MERR_CNT_LEN    32
#define DMC_MERR_CNT_OFFSET 0

#define DMC_FLUX_WR_LEN    32
#define DMC_FLUX_WR_OFFSET 0

#define DMC_FLUX_RD_LEN    32
#define DMC_FLUX_RD_OFFSET 0

#define DMC_FLUX_WR_CMD_LEN    32
#define DMC_FLUX_WR_CMD_OFFSET 0

#define DMC_FLUX_RD_CMD_LEN    32
#define DMC_FLUX_RD_CMD_OFFSET 0

#define DMC_FLUXID_WR_LEN    32
#define DMC_FLUXID_WR_OFFSET 0

#define DMC_FLUXID_RD_LEN    32
#define DMC_FLUXID_RD_OFFSET 0

#define DMC_FLUXID_WR_CMD_LEN    32
#define DMC_FLUXID_WR_CMD_OFFSET 0

#define DMC_FLUXID_RD_CMD_LEN    32
#define DMC_FLUXID_RD_CMD_OFFSET 0

#define DMC_WLATCNT_MAX_LEN    16
#define DMC_WLATCNT_MAX_OFFSET 16
#define DMC_WLATCNT_MIN_LEN    16
#define DMC_WLATCNT_MIN_OFFSET 0

#define DMC_WLATCNT_ALL_LEN    32
#define DMC_WLATCNT_ALL_OFFSET 0

#define DMC_RLATCNT_MAX_LEN    16
#define DMC_RLATCNT_MAX_OFFSET 16
#define DMC_RLATCNT_MIN_LEN    16
#define DMC_RLATCNT_MIN_OFFSET 0

#define DMC_RLATCNT_ALL_LEN    32
#define DMC_RLATCNT_ALL_OFFSET 0

#define DMC_INHERE_RLATCNT_LEN    16
#define DMC_INHERE_RLATCNT_OFFSET 0

#define DMC_STAT_RPT_LEN    3
#define DMC_STAT_RPT_OFFSET 0

#define DMC_DMC_CMD_SUM_LEN    32
#define DMC_DMC_CMD_SUM_OFFSET 0

#define DMC_DMC_DAT_SUM_LEN    32
#define DMC_DMC_DAT_SUM_OFFSET 0

#define DMC_DMC_PRE_CMD_LEN    32
#define DMC_DMC_PRE_CMD_OFFSET 0

#define DMC_DMC_ACT_CMD_LEN    32
#define DMC_DMC_ACT_CMD_OFFSET 0

#define DMC_DMC_BNK_CHG_LEN    32
#define DMC_DMC_BNK_CHG_OFFSET 0

#define DMC_DMC_RNK_CHG_LEN    32
#define DMC_DMC_RNK_CHG_OFFSET 0

#define DMC_DMC_RW_CHG_LEN    32
#define DMC_DMC_RW_CHG_OFFSET 0

#define DMC_TMON_ERR_RANK1_BF_LEN    8
#define DMC_TMON_ERR_RANK1_BF_OFFSET 24
#define DMC_TMON_ERR_RANK0_BF_LEN    8
#define DMC_TMON_ERR_RANK0_BF_OFFSET 16
#define DMC_TMON_ERR_RANK1_LEN       8
#define DMC_TMON_ERR_RANK1_OFFSET    8
#define DMC_TMON_ERR_RANK0_LEN       8
#define DMC_TMON_ERR_RANK0_OFFSET    0

#define DMC_RERR_ADDRL_LEN    32
#define DMC_RERR_ADDRL_OFFSET 0

#define DMC_RERR_ADDRH_LEN    32
#define DMC_RERR_ADDRH_OFFSET 0

#define DMC_RERR_TYPE_LEN    1
#define DMC_RERR_TYPE_OFFSET 31
#define DMC_RERR_ID_LEN      31
#define DMC_RERR_ID_OFFSET   0

#define DMC_RERR_CNT_LEN    32
#define DMC_RERR_CNT_OFFSET 0

#define DMC_PARERR_CNT_LEN    16
#define DMC_PARERR_CNT_OFFSET 16
#define DMC_CRCERR_CNT_LEN    16
#define DMC_CRCERR_CNT_OFFSET 0

#define DMC_RESEVERD_LEN         10
#define DMC_RESEVERD_OFFSET      22
#define DMC_CRC_NO_WR_LEN        1
#define DMC_CRC_NO_WR_OFFSET     21
#define DMC_OVERNUM_ERR_LEN      1
#define DMC_OVERNUM_ERR_OFFSET   20
#define DMC_REC_CNT_LEN          4
#define DMC_REC_CNT_OFFSET       16
#define DMC_CRC_NO_WR_CNT_LEN    8
#define DMC_CRC_NO_WR_CNT_OFFSET 8
#define DMC_OVERNUM_CNT_LEN      8
#define DMC_OVERNUM_CNT_OFFSET   0

#define DMC_ITER_CNT_LEN          16
#define DMC_ITER_CNT_OFFSET       16
#define DMC_FINGERPRINT_LEN       4
#define DMC_FINGERPRINT_OFFSET    12
#define DMC_DIAG_IP_LEN           3
#define DMC_DIAG_IP_OFFSET        8
#define DMC_DIAG_FIFO_LAST_LEN    1
#define DMC_DIAG_FIFO_LAST_OFFSET 6
#define DMC_WATCHDOG_ERROR_LEN    1
#define DMC_WATCHDOG_ERROR_OFFSET 5
#define DMC_PARITY_ERROR_LEN      1
#define DMC_PARITY_ERROR_OFFSET   4
#define DMC_BIST_PASS_LEN         1
#define DMC_BIST_PASS_OFFSET      1
#define DMC_BIST_DONE_LEN         1
#define DMC_BIST_DONE_OFFSET      0

#define DMC_MTEST_ELEMENT_LEN    3
#define DMC_MTEST_ELEMENT_OFFSET 8
#define DMC_MTEST_BG_CNT_LEN     4
#define DMC_MTEST_BG_CNT_OFFSET  4
#define DMC_MTEST_ERR_LEN        1
#define DMC_MTEST_ERR_OFFSET     0

#define DMC_MTEST_ERR_ADDR_LEN    28
#define DMC_MTEST_ERR_ADDR_OFFSET 0

#define DMC_MTEST_EXP_DATA0_LEN    32
#define DMC_MTEST_EXP_DATA0_OFFSET 0

#define DMC_MTEST_EXP_DATA1_LEN    32
#define DMC_MTEST_EXP_DATA1_OFFSET 0

#define DMC_MTEST_EXP_DATA2_LEN    32
#define DMC_MTEST_EXP_DATA2_OFFSET 0

#define DMC_MTEST_EXP_DATA3_LEN    32
#define DMC_MTEST_EXP_DATA3_OFFSET 0

#define DMC_MTEST_EXP_DATA4_LEN    32
#define DMC_MTEST_EXP_DATA4_OFFSET 0

#define DMC_MTEST_EXP_DATA5_LEN    32
#define DMC_MTEST_EXP_DATA5_OFFSET 0

#define DMC_MTEST_EXP_DATA6_LEN    32
#define DMC_MTEST_EXP_DATA6_OFFSET 0

#define DMC_MTEST_EXP_DATA7_LEN    32
#define DMC_MTEST_EXP_DATA7_OFFSET 0

#define DMC_MTEST_EXP_DATA8_LEN    32
#define DMC_MTEST_EXP_DATA8_OFFSET 0

#define DMC_MTEST_EXP_DATA9_LEN    32
#define DMC_MTEST_EXP_DATA9_OFFSET 0

#define DMC_MTEST_EXP_DATA10_LEN    32
#define DMC_MTEST_EXP_DATA10_OFFSET 0

#define DMC_MTEST_EXP_DATA11_LEN    32
#define DMC_MTEST_EXP_DATA11_OFFSET 0

#define DMC_MTEST_EXP_DATA12_LEN    32
#define DMC_MTEST_EXP_DATA12_OFFSET 0

#define DMC_MTEST_EXP_DATA13_LEN    32
#define DMC_MTEST_EXP_DATA13_OFFSET 0

#define DMC_MTEST_EXP_DATA14_LEN    32
#define DMC_MTEST_EXP_DATA14_OFFSET 0

#define DMC_MTEST_EXP_DATA15_LEN    32
#define DMC_MTEST_EXP_DATA15_OFFSET 0

#define DMC_MTEST_EXP_DATA16_LEN    32
#define DMC_MTEST_EXP_DATA16_OFFSET 0

#define DMC_MTEST_EXP_DATA17_LEN    32
#define DMC_MTEST_EXP_DATA17_OFFSET 0

#define DMC_MTEST_ERR_DATA0_LEN    32
#define DMC_MTEST_ERR_DATA0_OFFSET 0

#define DMC_MTEST_ERR_DATA1_LEN    32
#define DMC_MTEST_ERR_DATA1_OFFSET 0

#define DMC_MTEST_ERR_DATA2_LEN    32
#define DMC_MTEST_ERR_DATA2_OFFSET 0

#define DMC_MTEST_ERR_DATA3_LEN    32
#define DMC_MTEST_ERR_DATA3_OFFSET 0

#define DMC_MTEST_ERR_DATA4_LEN    32
#define DMC_MTEST_ERR_DATA4_OFFSET 0

#define DMC_MTEST_ERR_DATA5_LEN    32
#define DMC_MTEST_ERR_DATA5_OFFSET 0

#define DMC_MTEST_ERR_DATA6_LEN    32
#define DMC_MTEST_ERR_DATA6_OFFSET 0

#define DMC_MTEST_ERR_DATA7_LEN    32
#define DMC_MTEST_ERR_DATA7_OFFSET 0

#define DMC_MTEST_ERR_DATA8_LEN    32
#define DMC_MTEST_ERR_DATA8_OFFSET 0

#define DMC_MTEST_ERR_DATA9_LEN    32
#define DMC_MTEST_ERR_DATA9_OFFSET 0

#define DMC_MTEST_ERR_DATA10_LEN    32
#define DMC_MTEST_ERR_DATA10_OFFSET 0

#define DMC_MTEST_ERR_DATA11_LEN    32
#define DMC_MTEST_ERR_DATA11_OFFSET 0

#define DMC_MTEST_ERR_DATA12_LEN    32
#define DMC_MTEST_ERR_DATA12_OFFSET 0

#define DMC_MTEST_ERR_DATA13_LEN    32
#define DMC_MTEST_ERR_DATA13_OFFSET 0

#define DMC_MTEST_ERR_DATA14_LEN    32
#define DMC_MTEST_ERR_DATA14_OFFSET 0

#define DMC_MTEST_ERR_DATA15_LEN    32
#define DMC_MTEST_ERR_DATA15_OFFSET 0

#define DMC_MTEST_ERR_DATA16_LEN    32
#define DMC_MTEST_ERR_DATA16_OFFSET 0

#define DMC_MTEST_ERR_DATA17_LEN    32
#define DMC_MTEST_ERR_DATA17_OFFSET 0

#define DMC_RDATA_LEN    32
#define DMC_RDATA_OFFSET 0

#define DMC_SFC_RDATA_PTR_LEN    32
#define DMC_SFC_RDATA_PTR_OFFSET 0

#define DMC_RDATA0_DBI_LEN    32
#define DMC_RDATA0_DBI_OFFSET 0

#define DMC_RDATA1_DBI_LEN    32
#define DMC_RDATA1_DBI_OFFSET 0

#define DMC_RDATA_ECC_DBI_LEN    32
#define DMC_RDATA_ECC_DBI_OFFSET 0

#define DMC_PSTPND_CNT_RNK1_LEN       4
#define DMC_PSTPND_CNT_RNK1_OFFSET    20
#define DMC_PSTPND_CNT_RNK0_LEN       4
#define DMC_PSTPND_CNT_RNK0_OFFSET    16
#define DMC_FMAIN_SREF_REF_VLD_LEN    4
#define DMC_FMAIN_SREF_REF_VLD_OFFSET 8
#define DMC_FMAIN_AREF_ACK_LEN        4
#define DMC_FMAIN_AREF_ACK_OFFSET     4
#define DMC_AREF_FMAIN_REF_REQ_LEN    4
#define DMC_AREF_FMAIN_REF_REQ_OFFSET 0

#define DMC_PHYUPD_IN_MAX_LEN         16
#define DMC_PHYUPD_IN_MAX_OFFSET      16
#define DMC_FMAIN_SRX_ACK_LEN         4
#define DMC_FMAIN_SRX_ACK_OFFSET      12
#define DMC_FMAIN_SRE_ACK_LEN         4
#define DMC_FMAIN_SRE_ACK_OFFSET      8
#define DMC_SREF_FMAIN_SRX_REQ_LEN    4
#define DMC_SREF_FMAIN_SRX_REQ_OFFSET 4
#define DMC_SREF_FMAIN_SRE_REQ_LEN    4
#define DMC_SREF_FMAIN_SRE_REQ_OFFSET 0

#define DMC_PHYUPD_OUT_MAX_LEN       16
#define DMC_PHYUPD_OUT_MAX_OFFSET    16
#define DMC_PD_FARB_CKE_LEN          4
#define DMC_PD_FARB_CKE_OFFSET       12
#define DMC_FMAIN_PD_ACK_LEN         4
#define DMC_FMAIN_PD_ACK_OFFSET      8
#define DMC_FMAIN_PD_EXIT_REQ_LEN    4
#define DMC_FMAIN_PD_EXIT_REQ_OFFSET 4
#define DMC_PD_FMAIN_PDEX_REQ_LEN    4
#define DMC_PD_FMAIN_PDEX_REQ_OFFSET 0

#define DMC_FUNC_BP_MAX_RNK0_LEN    20
#define DMC_FUNC_BP_MAX_RNK0_OFFSET 12
#define DMC_FMAIN_SFC_ACK_LEN       4
#define DMC_FMAIN_SFC_ACK_OFFSET    4
#define DMC_SFC_FMAIN_REQ_LEN       4
#define DMC_SFC_FMAIN_REQ_OFFSET    0

#define DMC_FUNC_BP_MAX_RNK1_LEN        20
#define DMC_FUNC_BP_MAX_RNK1_OFFSET     12
#define DMC_FMAIN_PHYUPD_BP_ACK_LEN     4
#define DMC_FMAIN_PHYUPD_BP_ACK_OFFSET  8
#define DMC_PHYUPD_FMAIN_PRE_REQ_LEN    4
#define DMC_PHYUPD_FMAIN_PRE_REQ_OFFSET 4
#define DMC_PHYUPD_FMAIN_BP_REQ_LEN     4
#define DMC_PHYUPD_FMAIN_BP_REQ_OFFSET  0

#define DMC_FMAIN_ZQ_ZQLATCH_ACK_LEN    4
#define DMC_FMAIN_ZQ_ZQLATCH_ACK_OFFSET 12
#define DMC_FMAIN_ZQ_ZQSTART_ACK_LEN    4
#define DMC_FMAIN_ZQ_ZQSTART_ACK_OFFSET 8
#define DMC_ZQ_FMAIN_ZQLATCH_REQ_LEN    4
#define DMC_ZQ_FMAIN_ZQLATCH_REQ_OFFSET 4
#define DMC_ZQ_FMAIN_ZQSTART_REQ_LEN    4
#define DMC_ZQ_FMAIN_ZQSTART_REQ_OFFSET 0

#define DMC_LP_STATE_LEN                3
#define DMC_LP_STATE_OFFSET             16
#define DMC_FMAIN_OSC_OSCMRR_ACK_LEN    4
#define DMC_FMAIN_OSC_OSCMRR_ACK_OFFSET 12
#define DMC_FMAIN_OSC_OSCMPC_ACK_LEN    4
#define DMC_FMAIN_OSC_OSCMPC_ACK_OFFSET 8
#define DMC_OSC_FMAIN_OSCMRR_REQ_LEN    4
#define DMC_OSC_FMAIN_OSCMRR_REQ_OFFSET 4
#define DMC_OSC_FMAIN_OSCMPC_REQ_LEN    4
#define DMC_OSC_FMAIN_OSCMPC_REQ_OFFSET 0

#define DMC_FMAIN_RET_ACK_LEN        4
#define DMC_FMAIN_RET_ACK_OFFSET     16
#define DMC_FMAIN_DUM_ACK_LEN        4
#define DMC_FMAIN_DUM_ACK_OFFSET     12
#define DMC_RET_FMAIN_MPC_REQ_LEN    4
#define DMC_RET_FMAIN_MPC_REQ_OFFSET 8
#define DMC_DUM_FMAIN_MPC_REQ_LEN    4
#define DMC_DUM_FMAIN_MPC_REQ_OFFSET 4
#define DMC_DUM_FMAIN_MRR_REQ_LEN    4
#define DMC_DUM_FMAIN_MRR_REQ_OFFSET 0

#define DMC_SREF_STATE_RNK1_LEN       4
#define DMC_SREF_STATE_RNK1_OFFSET    20
#define DMC_SREF_STATE_RNK0_LEN       4
#define DMC_SREF_STATE_RNK0_OFFSET    16
#define DMC_FMAIN_TMON_ACK_LEN        4
#define DMC_FMAIN_TMON_ACK_OFFSET     4
#define DMC_TMON_FMAIN_MRR_REQ_LEN    4
#define DMC_TMON_FMAIN_MRR_REQ_OFFSET 0

#define DMC_DUMRD_STATE_RNK3_LEN    4
#define DMC_DUMRD_STATE_RNK3_OFFSET 28
#define DMC_DUMRD_STATE_RNK2_LEN    4
#define DMC_DUMRD_STATE_RNK2_OFFSET 24
#define DMC_DUMRD_STATE_RNK1_LEN    4
#define DMC_DUMRD_STATE_RNK1_OFFSET 20
#define DMC_DUMRD_STATE_RNK0_LEN    4
#define DMC_DUMRD_STATE_RNK0_OFFSET 16
#define DMC_AREF_STATE_RNK3_LEN     4
#define DMC_AREF_STATE_RNK3_OFFSET  12
#define DMC_AREF_STATE_RNK2_LEN     4
#define DMC_AREF_STATE_RNK2_OFFSET  8
#define DMC_AREFSTATE_RNK1_LEN      4
#define DMC_AREFSTATE_RNK1_OFFSET   4
#define DMC_AREF_STATE_RNK0_LEN     4
#define DMC_AREF_STATE_RNK0_OFFSET  0

#define DMC_OSC_STATE_RNK3_LEN    4
#define DMC_OSC_STATE_RNK3_OFFSET 28
#define DMC_OSC_STATE_RNK2_LEN    4
#define DMC_OSC_STATE_RNK2_OFFSET 24
#define DMC_OSC_STATE_RNK1_LEN    4
#define DMC_OSC_STATE_RNK1_OFFSET 20
#define DMC_OSC_STATE_RNK0_LEN    4
#define DMC_OSC_STATE_RNK0_OFFSET 16
#define DMC_PD_STATE_RNK3_LEN     4
#define DMC_PD_STATE_RNK3_OFFSET  12
#define DMC_PD_STATE_RNK2_LEN     4
#define DMC_PD_STATE_RNK2_OFFSET  8
#define DMC_PD_STATE_RNK1_LEN     4
#define DMC_PD_STATE_RNK1_OFFSET  4
#define DMC_PD_STATE_RNK0_LEN     4
#define DMC_PD_STATE_RNK0_OFFSET  0

#define DMC_OCFG_PHYUPD_STATE_LEN    4
#define DMC_OCFG_PHYUPD_STATE_OFFSET 25
#define DMC_OCFG_SFC_STATE_LEN       5
#define DMC_OCFG_SFC_STATE_OFFSET    20
#define DMC_OCFG_ZQ_STATE_LEN        4
#define DMC_OCFG_ZQ_STATE_OFFSET     16
#define DMC_TMON_STATE_RNK3_LEN      4
#define DMC_TMON_STATE_RNK3_OFFSET   12
#define DMC_TMON_STATE_RNK2_LEN      4
#define DMC_TMON_STATE_RNK2_OFFSET   8
#define DMC_TMON_STATE_RNK1_LEN      4
#define DMC_TMON_STATE_RNK1_OFFSET   4
#define DMC_TMON_STATE_RNK0_LEN      4
#define DMC_TMON_STATE_RNK0_OFFSET   0

#define DMC_RP_FIFO_EMPTY_LEN    1
#define DMC_RP_FIFO_EMPTY_OFFSET 3
#define DMC_RP_FIFO_FULL_LEN     1
#define DMC_RP_FIFO_FULL_OFFSET  2
#define DMC_SB_FIFO_EMPTY_LEN    1
#define DMC_SB_FIFO_EMPTY_OFFSET 1
#define DMC_SB_FIFO_FULL_LEN     1
#define DMC_SB_FIFO_FULL_OFFSET  0

#define DMC_RAM_TMOD_LEN    32
#define DMC_RAM_TMOD_OFFSET 0

#define DMC_MDDRC_CFIFO_NUM_LEN      8
#define DMC_MDDRC_CFIFO_NUM_OFFSET   24
#define DMC_MDDRC_ECC_WIDTH_LEN      4
#define DMC_MDDRC_ECC_WIDTH_OFFSET   20
#define DMC_MDDRC_DMC_WIDTH_LEN      4
#define DMC_MDDRC_DMC_WIDTH_OFFSET   16
#define DMC_MDDRC_DMC_VERSION_LEN    16
#define DMC_MDDRC_DMC_VERSION_OFFSET 0

#define DMC_MDDRC_MBIST_TYPE_LEN      2
#define DMC_MDDRC_MBIST_TYPE_OFFSET   24
#define DMC_MDDRC_BANK_XOR_POS_LEN    5
#define DMC_MDDRC_BANK_XOR_POS_OFFSET 16
#define DMC_MDDRC_PHY_TYPE_LEN        8
#define DMC_MDDRC_PHY_TYPE_OFFSET     8
#define DMC_MDDRC_ADDR_WIDTH_LEN      4
#define DMC_MDDRC_ADDR_WIDTH_OFFSET   4
#define DMC_MDDRC_RANK_NUM_LEN        4
#define DMC_MDDRC_RANK_NUM_OFFSET     0

#define DMC_MDDRC_DASW_PIPE_EN_LEN    1
#define DMC_MDDRC_DASW_PIPE_EN_OFFSET 10
#define DMC_MDDRC_HDR_MODE_LEN        2
#define DMC_MDDRC_HDR_MODE_OFFSET     8
#define DMC_MDDRC_REC_EN_LEN          1
#define DMC_MDDRC_REC_EN_OFFSET       7
#define DMC_MDDRC_RAM_ECC_EN_LEN      1
#define DMC_MDDRC_RAM_ECC_EN_OFFSET   6
#define DMC_MDDRC_CRC_PIPE_EN_LEN     1
#define DMC_MDDRC_CRC_PIPE_EN_OFFSET  5
#define DMC_MDDRC_DEBUG_BUS_LEN       1
#define DMC_MDDRC_DEBUG_BUS_OFFSET    4
#define DMC_MDDRC_ECC_EN_LEN          1
#define DMC_MDDRC_ECC_EN_OFFSET       3
#define DMC_MDDRC_PHY_IN_FLOP_LEN     1
#define DMC_MDDRC_PHY_IN_FLOP_OFFSET  2
#define DMC_MDDRC_FFBYP_EN_LEN        1
#define DMC_MDDRC_FFBYP_EN_OFFSET     1
#define DMC_MDDRC_RLAST_EN_LEN        1
#define DMC_MDDRC_RLAST_EN_OFFSET     0

#define DMC_OSC_COUNT_BASE_0_LEN    16
#define DMC_OSC_COUNT_BASE_0_OFFSET 16
#define DMC_OSC_COUNT_0_LEN         16
#define DMC_OSC_COUNT_0_OFFSET      0

#define DMC_OSC_COUNT_BASE_1_LEN    16
#define DMC_OSC_COUNT_BASE_1_OFFSET 16
#define DMC_OSC_COUNT_1_LEN         16
#define DMC_OSC_COUNT_1_OFFSET      0

#define DMC_OSC_COUNT_BASE_2_LEN    16
#define DMC_OSC_COUNT_BASE_2_OFFSET 16
#define DMC_OSC_COUNT_2_LEN         16
#define DMC_OSC_COUNT_2_OFFSET      0

#define DMC_OSC_COUNT_BASE_3_LEN    16
#define DMC_OSC_COUNT_BASE_3_OFFSET 16
#define DMC_OSC_COUNT_3_LEN         16
#define DMC_OSC_COUNT_3_OFFSET      0

#define DMC_OSC_COUNT_BASE_4_LEN    16
#define DMC_OSC_COUNT_BASE_4_OFFSET 16
#define DMC_OSC_COUNT_4_LEN         16
#define DMC_OSC_COUNT_4_OFFSET      0

#define DMC_OSC_COUNT_BASE_5_LEN    16
#define DMC_OSC_COUNT_BASE_5_OFFSET 16
#define DMC_OSC_COUNT_5_LEN         16
#define DMC_OSC_COUNT_5_OFFSET      0

#define DMC_OSC_COUNT_BASE_6_LEN    16
#define DMC_OSC_COUNT_BASE_6_OFFSET 16
#define DMC_OSC_COUNT_6_LEN         16
#define DMC_OSC_COUNT_6_OFFSET      0

#define DMC_OSC_COUNT_BASE_7_LEN    16
#define DMC_OSC_COUNT_BASE_7_OFFSET 16
#define DMC_OSC_COUNT_7_LEN         16
#define DMC_OSC_COUNT_7_OFFSET      0

#define DMC_OSC_COUNT_BASE_8_LEN    16
#define DMC_OSC_COUNT_BASE_8_OFFSET 16
#define DMC_OSC_COUNT_8_LEN         16
#define DMC_OSC_COUNT_8_OFFSET      0

#define DMC_OSC_COUNT_BASE_9_LEN    16
#define DMC_OSC_COUNT_BASE_9_OFFSET 16
#define DMC_OSC_COUNT_9_LEN         16
#define DMC_OSC_COUNT_9_OFFSET      0

#define DMC_OSC_COUNT_BASE_10_LEN    16
#define DMC_OSC_COUNT_BASE_10_OFFSET 16
#define DMC_OSC_COUNT_10_LEN         16
#define DMC_OSC_COUNT_10_OFFSET      0

#define DMC_OSC_COUNT_BASE_11_LEN    16
#define DMC_OSC_COUNT_BASE_11_OFFSET 16
#define DMC_OSC_COUNT_11_LEN         16
#define DMC_OSC_COUNT_11_OFFSET      0

#define DMC_OSC_COUNT_BASE_12_LEN    16
#define DMC_OSC_COUNT_BASE_12_OFFSET 16
#define DMC_OSC_COUNT_12_LEN         16
#define DMC_OSC_COUNT_12_OFFSET      0

#define DMC_OSC_COUNT_BASE_13_LEN    16
#define DMC_OSC_COUNT_BASE_13_OFFSET 16
#define DMC_OSC_COUNT_13_LEN         16
#define DMC_OSC_COUNT_13_OFFSET      0

#define DMC_OSC_COUNT_BASE_14_LEN    16
#define DMC_OSC_COUNT_BASE_14_OFFSET 16
#define DMC_OSC_COUNT_14_LEN         16
#define DMC_OSC_COUNT_14_OFFSET      0

#define DMC_OSC_COUNT_BASE_15_LEN    16
#define DMC_OSC_COUNT_BASE_15_OFFSET 16
#define DMC_OSC_COUNT_15_LEN         16
#define DMC_OSC_COUNT_15_OFFSET      0

#define DMC_TLP_WAKEUP_L2_LEN       4
#define DMC_TLP_WAKEUP_L2_OFFSET    16
#define DMC_TLP_WAKEUP_L3_LEN       4
#define DMC_TLP_WAKEUP_L3_OFFSET    8
#define DMC_DYN_LP_WAKEUP_EN_LEN    1
#define DMC_DYN_LP_WAKEUP_EN_OFFSET 0

#define DMC_LP_L2_IDLE_LEN    20
#define DMC_LP_L2_IDLE_OFFSET 0

#define DMC_LP_L3_IDLE_LEN    20
#define DMC_LP_L3_IDLE_OFFSET 0

#define DMC_EDXN_DQ7_MAP_0_LEN    3
#define DMC_EDXN_DQ7_MAP_0_OFFSET 28
#define DMC_EDXN_DQ6_MAP_0_LEN    3
#define DMC_EDXN_DQ6_MAP_0_OFFSET 24
#define DMC_EDXN_DQ5_MAP_0_LEN    3
#define DMC_EDXN_DQ5_MAP_0_OFFSET 20
#define DMC_EDXN_DQ4_MAP_0_LEN    3
#define DMC_EDXN_DQ4_MAP_0_OFFSET 16
#define DMC_EDXN_DQ3_MAP_0_LEN    3
#define DMC_EDXN_DQ3_MAP_0_OFFSET 12
#define DMC_EDXN_DQ2_MAP_0_LEN    3
#define DMC_EDXN_DQ2_MAP_0_OFFSET 8
#define DMC_EDXN_DQ1_MAP_0_LEN    3
#define DMC_EDXN_DQ1_MAP_0_OFFSET 4
#define DMC_EDXN_DQ0_MAP_0_LEN    3
#define DMC_EDXN_DQ0_MAP_0_OFFSET 0

#define DMC_EDXN_DQ7_MAP_1_LEN    3
#define DMC_EDXN_DQ7_MAP_1_OFFSET 28
#define DMC_EDXN_DQ6_MAP_1_LEN    3
#define DMC_EDXN_DQ6_MAP_1_OFFSET 24
#define DMC_EDXN_DQ5_MAP_1_LEN    3
#define DMC_EDXN_DQ5_MAP_1_OFFSET 20
#define DMC_EDXN_DQ4_MAP_1_LEN    3
#define DMC_EDXN_DQ4_MAP_1_OFFSET 16
#define DMC_EDXN_DQ3_MAP_1_LEN    3
#define DMC_EDXN_DQ3_MAP_1_OFFSET 12
#define DMC_EDXN_DQ2_MAP_1_LEN    3
#define DMC_EDXN_DQ2_MAP_1_OFFSET 8
#define DMC_EDXN_DQ1_MAP_1_LEN    3
#define DMC_EDXN_DQ1_MAP_1_OFFSET 4
#define DMC_EDXN_DQ0_MAP_1_LEN    3
#define DMC_EDXN_DQ0_MAP_1_OFFSET 0

#define DMC_EDXN_DQ7_MAP_2_LEN    3
#define DMC_EDXN_DQ7_MAP_2_OFFSET 28
#define DMC_EDXN_DQ6_MAP_2_LEN    3
#define DMC_EDXN_DQ6_MAP_2_OFFSET 24
#define DMC_EDXN_DQ5_MAP_2_LEN    3
#define DMC_EDXN_DQ5_MAP_2_OFFSET 20
#define DMC_EDXN_DQ4_MAP_2_LEN    3
#define DMC_EDXN_DQ4_MAP_2_OFFSET 16
#define DMC_EDXN_DQ3_MAP_2_LEN    3
#define DMC_EDXN_DQ3_MAP_2_OFFSET 12
#define DMC_EDXN_DQ2_MAP_2_LEN    3
#define DMC_EDXN_DQ2_MAP_2_OFFSET 8
#define DMC_EDXN_DQ1_MAP_2_LEN    3
#define DMC_EDXN_DQ1_MAP_2_OFFSET 4
#define DMC_EDXN_DQ0_MAP_2_LEN    3
#define DMC_EDXN_DQ0_MAP_2_OFFSET 0

#define DMC_EDXN_DQ7_MAP_3_LEN    3
#define DMC_EDXN_DQ7_MAP_3_OFFSET 28
#define DMC_EDXN_DQ6_MAP_3_LEN    3
#define DMC_EDXN_DQ6_MAP_3_OFFSET 24
#define DMC_EDXN_DQ5_MAP_3_LEN    3
#define DMC_EDXN_DQ5_MAP_3_OFFSET 20
#define DMC_EDXN_DQ4_MAP_3_LEN    3
#define DMC_EDXN_DQ4_MAP_3_OFFSET 16
#define DMC_EDXN_DQ3_MAP_3_LEN    3
#define DMC_EDXN_DQ3_MAP_3_OFFSET 12
#define DMC_EDXN_DQ2_MAP_3_LEN    3
#define DMC_EDXN_DQ2_MAP_3_OFFSET 8
#define DMC_EDXN_DQ1_MAP_3_LEN    3
#define DMC_EDXN_DQ1_MAP_3_OFFSET 4
#define DMC_EDXN_DQ0_MAP_3_LEN    3
#define DMC_EDXN_DQ0_MAP_3_OFFSET 0

#define DMC_EDXN_DQ7_MAP_4_LEN    3
#define DMC_EDXN_DQ7_MAP_4_OFFSET 28
#define DMC_EDXN_DQ6_MAP_4_LEN    3
#define DMC_EDXN_DQ6_MAP_4_OFFSET 24
#define DMC_EDXN_DQ5_MAP_4_LEN    3
#define DMC_EDXN_DQ5_MAP_4_OFFSET 20
#define DMC_EDXN_DQ4_MAP_4_LEN    3
#define DMC_EDXN_DQ4_MAP_4_OFFSET 16
#define DMC_EDXN_DQ3_MAP_4_LEN    3
#define DMC_EDXN_DQ3_MAP_4_OFFSET 12
#define DMC_EDXN_DQ2_MAP_4_LEN    3
#define DMC_EDXN_DQ2_MAP_4_OFFSET 8
#define DMC_EDXN_DQ1_MAP_4_LEN    3
#define DMC_EDXN_DQ1_MAP_4_OFFSET 4
#define DMC_EDXN_DQ0_MAP_4_LEN    3
#define DMC_EDXN_DQ0_MAP_4_OFFSET 0

#define DMC_EDXN_DQ7_MAP_5_LEN    3
#define DMC_EDXN_DQ7_MAP_5_OFFSET 28
#define DMC_EDXN_DQ6_MAP_5_LEN    3
#define DMC_EDXN_DQ6_MAP_5_OFFSET 24
#define DMC_EDXN_DQ5_MAP_5_LEN    3
#define DMC_EDXN_DQ5_MAP_5_OFFSET 20
#define DMC_EDXN_DQ4_MAP_5_LEN    3
#define DMC_EDXN_DQ4_MAP_5_OFFSET 16
#define DMC_EDXN_DQ3_MAP_5_LEN    3
#define DMC_EDXN_DQ3_MAP_5_OFFSET 12
#define DMC_EDXN_DQ2_MAP_5_LEN    3
#define DMC_EDXN_DQ2_MAP_5_OFFSET 8
#define DMC_EDXN_DQ1_MAP_5_LEN    3
#define DMC_EDXN_DQ1_MAP_5_OFFSET 4
#define DMC_EDXN_DQ0_MAP_5_LEN    3
#define DMC_EDXN_DQ0_MAP_5_OFFSET 0

#define DMC_EDXN_DQ7_MAP_6_LEN    3
#define DMC_EDXN_DQ7_MAP_6_OFFSET 28
#define DMC_EDXN_DQ6_MAP_6_LEN    3
#define DMC_EDXN_DQ6_MAP_6_OFFSET 24
#define DMC_EDXN_DQ5_MAP_6_LEN    3
#define DMC_EDXN_DQ5_MAP_6_OFFSET 20
#define DMC_EDXN_DQ4_MAP_6_LEN    3
#define DMC_EDXN_DQ4_MAP_6_OFFSET 16
#define DMC_EDXN_DQ3_MAP_6_LEN    3
#define DMC_EDXN_DQ3_MAP_6_OFFSET 12
#define DMC_EDXN_DQ2_MAP_6_LEN    3
#define DMC_EDXN_DQ2_MAP_6_OFFSET 8
#define DMC_EDXN_DQ1_MAP_6_LEN    3
#define DMC_EDXN_DQ1_MAP_6_OFFSET 4
#define DMC_EDXN_DQ0_MAP_6_LEN    3
#define DMC_EDXN_DQ0_MAP_6_OFFSET 0

#define DMC_EDXN_DQ7_MAP_7_LEN    3
#define DMC_EDXN_DQ7_MAP_7_OFFSET 28
#define DMC_EDXN_DQ6_MAP_7_LEN    3
#define DMC_EDXN_DQ6_MAP_7_OFFSET 24
#define DMC_EDXN_DQ5_MAP_7_LEN    3
#define DMC_EDXN_DQ5_MAP_7_OFFSET 20
#define DMC_EDXN_DQ4_MAP_7_LEN    3
#define DMC_EDXN_DQ4_MAP_7_OFFSET 16
#define DMC_EDXN_DQ3_MAP_7_LEN    3
#define DMC_EDXN_DQ3_MAP_7_OFFSET 12
#define DMC_EDXN_DQ2_MAP_7_LEN    3
#define DMC_EDXN_DQ2_MAP_7_OFFSET 8
#define DMC_EDXN_DQ1_MAP_7_LEN    3
#define DMC_EDXN_DQ1_MAP_7_OFFSET 4
#define DMC_EDXN_DQ0_MAP_7_LEN    3
#define DMC_EDXN_DQ0_MAP_7_OFFSET 0

#define DMC_EDXN_DQ7_MAP_8_LEN    3
#define DMC_EDXN_DQ7_MAP_8_OFFSET 28
#define DMC_EDXN_DQ6_MAP_8_LEN    3
#define DMC_EDXN_DQ6_MAP_8_OFFSET 24
#define DMC_EDXN_DQ5_MAP_8_LEN    3
#define DMC_EDXN_DQ5_MAP_8_OFFSET 20
#define DMC_EDXN_DQ4_MAP_8_LEN    3
#define DMC_EDXN_DQ4_MAP_8_OFFSET 16
#define DMC_EDXN_DQ3_MAP_8_LEN    3
#define DMC_EDXN_DQ3_MAP_8_OFFSET 12
#define DMC_EDXN_DQ2_MAP_8_LEN    3
#define DMC_EDXN_DQ2_MAP_8_OFFSET 8
#define DMC_EDXN_DQ1_MAP_8_LEN    3
#define DMC_EDXN_DQ1_MAP_8_OFFSET 4
#define DMC_EDXN_DQ0_MAP_8_LEN    3
#define DMC_EDXN_DQ0_MAP_8_OFFSET 0

#define DMC_EDXN_DQ7_MAP_9_LEN    3
#define DMC_EDXN_DQ7_MAP_9_OFFSET 28
#define DMC_EDXN_DQ6_MAP_9_LEN    3
#define DMC_EDXN_DQ6_MAP_9_OFFSET 24
#define DMC_EDXN_DQ5_MAP_9_LEN    3
#define DMC_EDXN_DQ5_MAP_9_OFFSET 20
#define DMC_EDXN_DQ4_MAP_9_LEN    3
#define DMC_EDXN_DQ4_MAP_9_OFFSET 16
#define DMC_EDXN_DQ3_MAP_9_LEN    3
#define DMC_EDXN_DQ3_MAP_9_OFFSET 12
#define DMC_EDXN_DQ2_MAP_9_LEN    3
#define DMC_EDXN_DQ2_MAP_9_OFFSET 8
#define DMC_EDXN_DQ1_MAP_9_LEN    3
#define DMC_EDXN_DQ1_MAP_9_OFFSET 4
#define DMC_EDXN_DQ0_MAP_9_LEN    3
#define DMC_EDXN_DQ0_MAP_9_OFFSET 0

#define DMC_ODXN_DQ7_MAP_0_LEN    3
#define DMC_ODXN_DQ7_MAP_0_OFFSET 28
#define DMC_ODXN_DQ6_MAP_0_LEN    3
#define DMC_ODXN_DQ6_MAP_0_OFFSET 24
#define DMC_ODXN_DQ5_MAP_0_LEN    3
#define DMC_ODXN_DQ5_MAP_0_OFFSET 20
#define DMC_ODXN_DQ4_MAP_0_LEN    3
#define DMC_ODXN_DQ4_MAP_0_OFFSET 16
#define DMC_ODXN_DQ3_MAP_0_LEN    3
#define DMC_ODXN_DQ3_MAP_0_OFFSET 12
#define DMC_ODXN_DQ2_MAP_0_LEN    3
#define DMC_ODXN_DQ2_MAP_0_OFFSET 8
#define DMC_ODXN_DQ1_MAP_0_LEN    3
#define DMC_ODXN_DQ1_MAP_0_OFFSET 4
#define DMC_ODXN_DQ0_MAP_0_LEN    3
#define DMC_ODXN_DQ0_MAP_0_OFFSET 0

#define DMC_ODXN_DQ7_MAP_1_LEN    3
#define DMC_ODXN_DQ7_MAP_1_OFFSET 28
#define DMC_ODXN_DQ6_MAP_1_LEN    3
#define DMC_ODXN_DQ6_MAP_1_OFFSET 24
#define DMC_ODXN_DQ5_MAP_1_LEN    3
#define DMC_ODXN_DQ5_MAP_1_OFFSET 20
#define DMC_ODXN_DQ4_MAP_1_LEN    3
#define DMC_ODXN_DQ4_MAP_1_OFFSET 16
#define DMC_ODXN_DQ3_MAP_1_LEN    3
#define DMC_ODXN_DQ3_MAP_1_OFFSET 12
#define DMC_ODXN_DQ2_MAP_1_LEN    3
#define DMC_ODXN_DQ2_MAP_1_OFFSET 8
#define DMC_ODXN_DQ1_MAP_1_LEN    3
#define DMC_ODXN_DQ1_MAP_1_OFFSET 4
#define DMC_ODXN_DQ0_MAP_1_LEN    3
#define DMC_ODXN_DQ0_MAP_1_OFFSET 0

#define DMC_ODXN_DQ7_MAP_2_LEN    3
#define DMC_ODXN_DQ7_MAP_2_OFFSET 28
#define DMC_ODXN_DQ6_MAP_2_LEN    3
#define DMC_ODXN_DQ6_MAP_2_OFFSET 24
#define DMC_ODXN_DQ5_MAP_2_LEN    3
#define DMC_ODXN_DQ5_MAP_2_OFFSET 20
#define DMC_ODXN_DQ4_MAP_2_LEN    3
#define DMC_ODXN_DQ4_MAP_2_OFFSET 16
#define DMC_ODXN_DQ3_MAP_2_LEN    3
#define DMC_ODXN_DQ3_MAP_2_OFFSET 12
#define DMC_ODXN_DQ2_MAP_2_LEN    3
#define DMC_ODXN_DQ2_MAP_2_OFFSET 8
#define DMC_ODXN_DQ1_MAP_2_LEN    3
#define DMC_ODXN_DQ1_MAP_2_OFFSET 4
#define DMC_ODXN_DQ0_MAP_2_LEN    3
#define DMC_ODXN_DQ0_MAP_2_OFFSET 0

#define DMC_ODXN_DQ7_MAP_3_LEN    3
#define DMC_ODXN_DQ7_MAP_3_OFFSET 28
#define DMC_ODXN_DQ6_MAP_3_LEN    3
#define DMC_ODXN_DQ6_MAP_3_OFFSET 24
#define DMC_ODXN_DQ5_MAP_3_LEN    3
#define DMC_ODXN_DQ5_MAP_3_OFFSET 20
#define DMC_ODXN_DQ4_MAP_3_LEN    3
#define DMC_ODXN_DQ4_MAP_3_OFFSET 16
#define DMC_ODXN_DQ3_MAP_3_LEN    3
#define DMC_ODXN_DQ3_MAP_3_OFFSET 12
#define DMC_ODXN_DQ2_MAP_3_LEN    3
#define DMC_ODXN_DQ2_MAP_3_OFFSET 8
#define DMC_ODXN_DQ1_MAP_3_LEN    3
#define DMC_ODXN_DQ1_MAP_3_OFFSET 4
#define DMC_ODXN_DQ0_MAP_3_LEN    3
#define DMC_ODXN_DQ0_MAP_3_OFFSET 0

#define DMC_ODXN_DQ7_MAP_4_LEN    3
#define DMC_ODXN_DQ7_MAP_4_OFFSET 28
#define DMC_ODXN_DQ6_MAP_4_LEN    3
#define DMC_ODXN_DQ6_MAP_4_OFFSET 24
#define DMC_ODXN_DQ5_MAP_4_LEN    3
#define DMC_ODXN_DQ5_MAP_4_OFFSET 20
#define DMC_ODXN_DQ4_MAP_4_LEN    3
#define DMC_ODXN_DQ4_MAP_4_OFFSET 16
#define DMC_ODXN_DQ3_MAP_4_LEN    3
#define DMC_ODXN_DQ3_MAP_4_OFFSET 12
#define DMC_ODXN_DQ2_MAP_4_LEN    3
#define DMC_ODXN_DQ2_MAP_4_OFFSET 8
#define DMC_ODXN_DQ1_MAP_4_LEN    3
#define DMC_ODXN_DQ1_MAP_4_OFFSET 4
#define DMC_ODXN_DQ0_MAP_4_LEN    3
#define DMC_ODXN_DQ0_MAP_4_OFFSET 0

#define DMC_ODXN_DQ7_MAP_5_LEN    3
#define DMC_ODXN_DQ7_MAP_5_OFFSET 28
#define DMC_ODXN_DQ6_MAP_5_LEN    3
#define DMC_ODXN_DQ6_MAP_5_OFFSET 24
#define DMC_ODXN_DQ5_MAP_5_LEN    3
#define DMC_ODXN_DQ5_MAP_5_OFFSET 20
#define DMC_ODXN_DQ4_MAP_5_LEN    3
#define DMC_ODXN_DQ4_MAP_5_OFFSET 16
#define DMC_ODXN_DQ3_MAP_5_LEN    3
#define DMC_ODXN_DQ3_MAP_5_OFFSET 12
#define DMC_ODXN_DQ2_MAP_5_LEN    3
#define DMC_ODXN_DQ2_MAP_5_OFFSET 8
#define DMC_ODXN_DQ1_MAP_5_LEN    3
#define DMC_ODXN_DQ1_MAP_5_OFFSET 4
#define DMC_ODXN_DQ0_MAP_5_LEN    3
#define DMC_ODXN_DQ0_MAP_5_OFFSET 0

#define DMC_ODXN_DQ7_MAP_6_LEN    3
#define DMC_ODXN_DQ7_MAP_6_OFFSET 28
#define DMC_ODXN_DQ6_MAP_6_LEN    3
#define DMC_ODXN_DQ6_MAP_6_OFFSET 24
#define DMC_ODXN_DQ5_MAP_6_LEN    3
#define DMC_ODXN_DQ5_MAP_6_OFFSET 20
#define DMC_ODXN_DQ4_MAP_6_LEN    3
#define DMC_ODXN_DQ4_MAP_6_OFFSET 16
#define DMC_ODXN_DQ3_MAP_6_LEN    3
#define DMC_ODXN_DQ3_MAP_6_OFFSET 12
#define DMC_ODXN_DQ2_MAP_6_LEN    3
#define DMC_ODXN_DQ2_MAP_6_OFFSET 8
#define DMC_ODXN_DQ1_MAP_6_LEN    3
#define DMC_ODXN_DQ1_MAP_6_OFFSET 4
#define DMC_ODXN_DQ0_MAP_6_LEN    3
#define DMC_ODXN_DQ0_MAP_6_OFFSET 0

#define DMC_ODXN_DQ7_MAP_7_LEN    3
#define DMC_ODXN_DQ7_MAP_7_OFFSET 28
#define DMC_ODXN_DQ6_MAP_7_LEN    3
#define DMC_ODXN_DQ6_MAP_7_OFFSET 24
#define DMC_ODXN_DQ5_MAP_7_LEN    3
#define DMC_ODXN_DQ5_MAP_7_OFFSET 20
#define DMC_ODXN_DQ4_MAP_7_LEN    3
#define DMC_ODXN_DQ4_MAP_7_OFFSET 16
#define DMC_ODXN_DQ3_MAP_7_LEN    3
#define DMC_ODXN_DQ3_MAP_7_OFFSET 12
#define DMC_ODXN_DQ2_MAP_7_LEN    3
#define DMC_ODXN_DQ2_MAP_7_OFFSET 8
#define DMC_ODXN_DQ1_MAP_7_LEN    3
#define DMC_ODXN_DQ1_MAP_7_OFFSET 4
#define DMC_ODXN_DQ0_MAP_7_LEN    3
#define DMC_ODXN_DQ0_MAP_7_OFFSET 0

#define DMC_ODXN_DQ7_MAP_8_LEN    3
#define DMC_ODXN_DQ7_MAP_8_OFFSET 28
#define DMC_ODXN_DQ6_MAP_8_LEN    3
#define DMC_ODXN_DQ6_MAP_8_OFFSET 24
#define DMC_ODXN_DQ5_MAP_8_LEN    3
#define DMC_ODXN_DQ5_MAP_8_OFFSET 20
#define DMC_ODXN_DQ4_MAP_8_LEN    3
#define DMC_ODXN_DQ4_MAP_8_OFFSET 16
#define DMC_ODXN_DQ3_MAP_8_LEN    3
#define DMC_ODXN_DQ3_MAP_8_OFFSET 12
#define DMC_ODXN_DQ2_MAP_8_LEN    3
#define DMC_ODXN_DQ2_MAP_8_OFFSET 8
#define DMC_ODXN_DQ1_MAP_8_LEN    3
#define DMC_ODXN_DQ1_MAP_8_OFFSET 4
#define DMC_ODXN_DQ0_MAP_8_LEN    3
#define DMC_ODXN_DQ0_MAP_8_OFFSET 0

#define DMC_ODXN_DQ7_MAP_9_LEN    3
#define DMC_ODXN_DQ7_MAP_9_OFFSET 28
#define DMC_ODXN_DQ6_MAP_9_LEN    3
#define DMC_ODXN_DQ6_MAP_9_OFFSET 24
#define DMC_ODXN_DQ5_MAP_9_LEN    3
#define DMC_ODXN_DQ5_MAP_9_OFFSET 20
#define DMC_ODXN_DQ4_MAP_9_LEN    3
#define DMC_ODXN_DQ4_MAP_9_OFFSET 16
#define DMC_ODXN_DQ3_MAP_9_LEN    3
#define DMC_ODXN_DQ3_MAP_9_OFFSET 12
#define DMC_ODXN_DQ2_MAP_9_LEN    3
#define DMC_ODXN_DQ2_MAP_9_OFFSET 8
#define DMC_ODXN_DQ1_MAP_9_LEN    3
#define DMC_ODXN_DQ1_MAP_9_OFFSET 4
#define DMC_ODXN_DQ0_MAP_9_LEN    3
#define DMC_ODXN_DQ0_MAP_9_OFFSET 0

#define DMC_DDR_RCMD_BL32_LEN    32
#define DMC_DDR_RCMD_BL32_OFFSET 0

#define DMC_DDR_WCMD_BL32_LEN    32
#define DMC_DDR_WCMD_BL32_OFFSET 0

#define DMC_DDR_RCMD_LEN    32
#define DMC_DDR_RCMD_OFFSET 0

#define DMC_DDR_WCMD_LEN    32
#define DMC_DDR_WCMD_OFFSET 0

#define DMC_REF_CMD_LEN    32
#define DMC_REF_CMD_OFFSET 0

#define DMC_PD_CNT_LEN    32
#define DMC_PD_CNT_OFFSET 0

#define DMC_ACT_PD_CNT_LEN    32
#define DMC_ACT_PD_CNT_OFFSET 0

#define DMC_ACT_NPD_CNT_LEN    32
#define DMC_ACT_NPD_CNT_OFFSET 0

#define DMC_RW_CHG_EN_LEN       1
#define DMC_RW_CHG_EN_OFFSET    8
#define DMC_RNK_CHG_EN_LEN      1
#define DMC_RNK_CHG_EN_OFFSET   7
#define DMC_ACT_CMD_EN_LEN      1
#define DMC_ACT_CMD_EN_OFFSET   5
#define DMC_PRE_CMD_EN_LEN      1
#define DMC_PRE_CMD_EN_OFFSET   4
#define DMC_FLUX_RCMD_EN_LEN    1
#define DMC_FLUX_RCMD_EN_OFFSET 3
#define DMC_FLUX_WCMD_EN_LEN    1
#define DMC_FLUX_WCMD_EN_OFFSET 2
#define DMC_FLUX_RD_EN_LEN      1
#define DMC_FLUX_RD_EN_OFFSET   1
#define DMC_FLUX_WR_EN_LEN      1
#define DMC_FLUX_WR_EN_OFFSET   0

#define DMC_PERF_INTR_LEN    9
#define DMC_PERF_INTR_OFFSET 0

#define DMC_PERF_INTM_LEN    9
#define DMC_PERF_INTM_OFFSET 0

#define DMC_PERF_INTS_LEN    9
#define DMC_PERF_INTS_OFFSET 0

#define DMC_PERF_INTC_LEN    9
#define DMC_PERF_INTC_OFFSET 0

#define DMC_IDLE_TH_LEN               8
#define DMC_IDLE_TH_OFFSET            16
#define DMC_CH_SYNC_IDLE_TH_LEN       8
#define DMC_CH_SYNC_IDLE_TH_OFFSET    8
#define DMC_CH_SYNC_PSTPND_LVL_LEN    3
#define DMC_CH_SYNC_PSTPND_LVL_OFFSET 4
#define DMC_CH_SYNC_EN_LEN            1
#define DMC_CH_SYNC_EN_OFFSET         0

#endif // __DMC_REG_OFFSET_FIELD_H__
